Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-26
2001-01-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S397000, C438S964000
Reexamination Certificate
active
06171903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the capacitor of dynamic random access memories (DRAMs), and more particularly to a method for forming a cylinder-shaped capacitor of the DRAMs using a dielectric hard mask.
2. Description of the Prior Art
As the semiconductor memory device becomes highly integrated, the area occupied by a capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
One approach for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this approach, the cylinder-shaped capacitor has become to be widely used in DRAM devices. However, especially for giga bit DRAM using 0.18 micrometer technology and beyond, the manufacture of the cylinder-shaped capacitor of such a small size becomes very difficult, if not impossible.
For the foregoing reasons, there is a need for a method of forming a cylinder-shaped capacitor for the DRAMs, and for facilitating the manufacture of cylinder-shaped capacitors.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a cylinder-shaped capacitor for dynamic random access memories (DRAMs) that substantially increases its surface area and therefore its capacitance. Particularly, the present invention provides a method for forming a cylinder-shaped capacitor, facilitating the fabrication of giga bit DRAMs using 0.18 micrometer technology and beyond. In one embodiment, the present invention includes firstly forming an amorphous silicon layer having a gap therein over a semiconductor substrate and conformably forming a first dielectric layer on the amorphous silicon layer. Next, a second dielectric layer is formed on the first dielectric layer, filling the gap. After etching back the second dielectric layer until the first dielectric layer is exposed, the first dielectric layer is removed until the amorphous silicon layer is exposed. Then the second dielectric layer is removed, followed by etching the amorphous silicon layer using the first dielectric layer as a mask, thus forming a cylinder-shaped structure over the substrate. Finally, a hemi-spherical-grain (HSG) layer is formed on the surface of the cylinder-shaped structure, thus resulting in a cylinder-shaped bottom plate with hemi-spherical grain for the capacitor of the dynamic random access memory.
REFERENCES:
patent: 5733808 (1998-03-01), Tseng
patent: 5960293 (1999-09-01), Hong et al.
patent: 6001682 (1999-12-01), Chien
patent: 6025246 (2000-02-01), Kim
patent: 6060366 (2000-05-01), Hong
H. Watanabe et al., “A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs”, IEDM Tech Dig., pp. 259-262, Dec. 1992.*
Harness & Dickey & Pierce P.L.C.
Kennedy Jennifer M.
Niebling John F.
United Microelectronics Corp.
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