Method for forming a contoured floating gate cell

Details Method for forming a contoured floating gate cell Method for forming a contoured floating gate cell

1999-10-08

2002-07-02

Sherry, Michael J. (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S263000, C438S270000, C438S593000, C438S594000

Reexamination Certificate

active

06413818

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile digital memory, and more particularly, to FLASH EPROM memory incorporating novel floating gates having reduced lateral dimensions.
2. Description of Related Art
FLASH EPROM memory is a class of non-volatile storage integrated circuits. In general, FLASH EPROMS have the capability of electrically erasing, programming, or reading a memory cell on a chip. Generally, a FLASH EPROM includes a floating gate and a control gate which form an electrical connection. A FLASH EPROM operates by charging or discharging electrons in the floating gate of the memory cell in a capacitive manner. The floating gate is formed of a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a layer of oxide or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed a Aprogram@ step for a FLASH EPROM. The program step may be accomplished through so-called hot electron injection by establishing a large positive voltage between the control gate and the source. The act of discharging the floating gate is called the Aerase@ function for a FLASH EPROM. The erase function is typically carried out by a Fowler-Nordhiem F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).
Due to increasing memory demands, a need exists to further reduce the size of memory devices, such as FLASH EPROMs. Reducing the cell size of memory devices increases performance and reduces power consumption.
Several devices have been developed with reduced cell size. One such device is described in “A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG,” by Kitamura et al., 1998
Symposium on VLSI Technology Digest of Technical Papers.
Another example of a memory device with reduced cell size is described in “A 0.24-Fm Cell Process With 0.18-Fm Width Isolation and 3D Interpoly Dielectric Films for 1-GB Flash Memories,” by Kobayashi et al., IEEE 97-275 (1997).
Reducing the size of a memory cell has led to memory cells with certain disadvantages including overbearing floating gates, or intermediate structures formed during the manufacturing of the floating gate, which degrade the tunnel oxide layer. The formation of sharp corners on the floating gate also leads to charge leakage.
SUMMARY OF THE INVENTION
A floating gate for use in a memory cell is provided which comprises a first end region positioned adjacent to a first lateral end of the floating gate, a second end region positioned adjacent to a second lateral end of the floating gate, and a middle region positioned laterally towards a middle of the floating gate relative to the first end region and the second end region. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region has a thickness which is less than a thickness of the first or second end regions.
According to another embodiment of the invention, a floating gate of a floating gate memory cell may include a first polysilicon layer formed during a first fabrication step, and a second polysilicon layer formed during a second fabrication over the first polysilicon layer. The second polysilicon layer may comprise a first end region positioned adjacent to a first lateral end of the floating gate, a second end region positioned adjacent to a second lateral end of the floating gate, and a middle region positioned laterally toward a middle of the floating gate relative to the first end region and the second end region.
In one variation, the first and second end regions each include an exterior surface forming an end of the floating gate, an interior surface adjacent to the middle region, a top end surface, and an interior surface adjacent to the middle region. In this embodiment, the end regions have a thickness that is substantially uniform between the exterior surface and the interior surface.
In another variation, the middle region may have a top surface that is substantially parallel to a substrate underlying the floating gate.
In another variation, the floating gate may have a bottom surface facing a plane of a substrate underlying the floating gate, where the floating gate is positioned substantially within a lateral footprint defined by the bottom surface of the floating gate.
In another variation, the floating gate is formed of a first layer of material formed during a first fabrication step, and a second layer of material formed over the first layer during a second fabrication step. Alternatively, the entire floating gate is formed during a single fabrication step.
Variations of the floating gate may also provide for the first exterior surfaces to be approximately perpendicular to the top end surfaces of the end regions, so that the interior surfaces are approximately perpendicular to the tangent plane to the top end surfaces of the end regions.
In regard to each of the above floating gate embodiments, the floating gate may be incorporated into a floating gate memory cell including a substrate, source and drain regions positioned over the substrate, and an insulating layer positioned over the source and drain regions. The floating gate is positioned over the insulating layer between the source and drain regions, and a control gate is positioned over the dielectric insulator.
Also provided according to the present invention are methods for fabricating the floating gates of the present invention. According to one embodiment, a method for forming a contoured floating gate for use in a floating gate memory cell is provided which includes forming a polysilicon layer over first and second spaced apart oxide structures, and over a floating gate region between the first and second oxide structures. The polysilicon layer formed in the floating gate region has a first end region adjacent the first oxide structure, a second end region adjacent the second oxide structure, and a middle region positioned laterally between the first and second end regions, the first and second end regions each having a vertical thickness greater than a vertical thickness of the middle region. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the first and second end regions remain greater than the vertical thickness of the middle region.
In another variation, the method further includes removing a portion of the first and second oxide structures so that the first end region and the second end region extend vertically beyond a top surface of the first and second oxide structures.
In another variation, forming a polysilicon layer over first and second oxide structures and a floating gate region includes forming the end regions to have a substantially uniform thickness between the exterior surfaces and the respective interior surfaces.
In another variation, removing the polysilicon layer over the first and second oxide structures includes planarizing the first oxide structure, second oxide structure, first end region and second end region.
In another method for fabricating a floating gate according to this invention, the method includes forming a first polysilicon layer in a floating gate region of a substrate. The method further includes forming oxide structures on opposing sides of the floating gate region, the first and second oxide structures having a vertical thickness greater than a vertical thickness of the first polysilicon layer. A second polysilicon layer is then formed over the first polysilicon layer and the oxide structures. The first and second polysilicon layers combine to form a floating gate in the floating gate region, the floating gate having a first end region adjacent to the first lateral end, a second end region a

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