Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
1999-03-12
2001-09-11
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S692000, C438S706000, C438S719000, C438S723000, C438S724000
Reexamination Certificate
active
06287971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and more particularly, to a method for forming a cell capacitor in a DRAM device.
2. Description of the Related Art
A memory device such as a DRAM in a semiconductor device includes a unit cell comprised of an access transistor and a cell capacitor. The cell capacitor has a structure in which a storage electrode in electrical connection with a source region (or a drain region) of the access transistor, a dielectric film and a plate electrode are sequentially stacked. The capacitance of the cell capacitor has a direct relation to the electrical characteristics and reliability of a DRAM cell. In other words, an increase in cell capacitance causes an increase in the period of a refresh signal for preventing disappearance of information stored in the DRAM cell, and a reduction in a soft error rate (SER) due to an á-particle. Accordingly, when the cell capacitance is increased, power consumption of the DRAM device can be reduced, and the reliability of the DRAM cell can be improved. However, as the integration of the DRAM device is increased, the area occupied by a cell is decreased. Many methods have been proposed for forming a cell capacitor having large capacitance within a limited area. Basically, in order to increase the capacitance of a cell capacitor formed within the limited area, the surface area of the storage electrode must be increased or a thin dielectric film must be formed between the storage and plate electrodes. Alternatively, the dielectric film can be formed of a material having a high dielectric constant. However, when the thin dielectric film is formed, leakage current characteristics of a capacitor is degraded. When the dielectric film is formed of a material having a high dielectric constant, the process for fabricating a capacitor is complicated. Recently, a method has been widely used for increasing the surface area of the storage electrode by increasing the height of the storage electrode.
FIGS. 1 and 3
are cross-sectional views illustrating a method for forming a conventional storage electrode.
Referring to
FIG. 1
, a plurality of isolation films
3
are formed in a predetermined region of a semiconductor substrate
1
. An interlayer insulating film
5
, e.g., a planarized silicon oxide film, is formed on the resultant structure on which the plurality of isolation films
3
are formed. The interlayer insulating film
5
is patterned to form a plurality of buried contact holes (H) for exposing active regions between the isolation films
3
. A DRAM cell bit line
7
can be formed inside the interlayer insulating film
5
.
Referring to
FIG. 2
, a conductive film, e.g., a doped polysilicon film, for filling the buried contact holes H is formed on the entire surface of the resultant structure on which the buried contact holes H are formed. The conductive film is patterned to form a plurality of storage electrodes
9
for covering the respective buried contact holes H. Here, the conductive film is formed by an over etch process, in order to prevent residues of the conductive film from existing between the storage electrodes
9
. Accordingly, as shown in
FIG. 2
, when mis-alignment occurs upon the photolithography for patterning the storage electrodes
9
, a part of the conductive film inside the buried contact holes H is etched to form grooves (G). When the grooves G are formed in this way, a portion where the horizontal section of the storage electrode
9
is narrow exists on the upper portion of the buried contact holes H.
FIG. 3
is a cross-sectional view illustrating the step of cleaning the surface of the storage electrode
9
. To be more specific, the resultant structure on which the storage electrodes
9
are formed is cleaned by a chemical solution, e.g., an oxide etchant to remove native oxide films formed on the surfaces of the storage electrodes
9
and contaminant particles. Here, the surface of the interlayer insulating film
5
is etched to form an undercut region under one edge of each of the storage electrodes
9
. Also, as shown in
FIG. 3
, the storage electrodes
9
are lifted off since the upper portion thereof is easily broken. The lifted storage electrodes
9
pollute the surface of the semiconductor substrate, causing an abnormal pattern and reducing the electrical isolation characteristics between the storage electrodes
9
.
According to the method for forming the conventional storage electrode as described above, when mis-alignment occurs upon the etch process for forming the storage electrode, the mid portion of the storage electrode has a narrow horizontal section. Thus, the storage electrodes are easily lifted, thereby contaminating the surface of the semiconductor substrate.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a method for forming a cell capacitor in a DRAM device, by which the surface of a semiconductor substrate can be prevented from being contaminated.
Accordingly, to achieve the above objective, in the present invention, a plug pattern in contact with a predetermined region of the semiconductor substrate is formed on the semiconductor substrate, and a storage electrode contacting the plug pattern is formed. Here, the storage electrode may contact the upper surface of the plug pattern, or the upper side walls and upper surface of the plug pattern.
According to an embodiment of the present invention, an interlayer insulating film is formed on a semiconductor substrate. First buried contact holes for exposing a predetermined region of the semiconductor substrate are formed by patterning the interlayer insulating film. Here, preferably, the interlayer insulating film is a planarized silicon oxide film, i.e., a film selected from the group consisting of doped silica glass and undoped silica glass. Alternatively, the interlayer insulating film may be comprised of the doped silica glass and the undoped silica glass. The doped silica glass can be either a BPSG film or a PSG film. A conductive film, e.g., a doped polysilicon film, for filling the first buried contact holes, is formed on the entire surface of the resultant structure on the first buried contact holes are formed. The conductive film is entirely etched until the interlayer insulating film is exposed, to form plug patterns in the first buried contact holes. It is preferable that the entire etching is performed using a chemical mechanical polishing (CMP) process. Then, an etch stop film, e.g., a silicon nitride film, is formed on the entire surface of the resultant structure on which the plug patterns are formed. The etch stop film is patterned to form second buried contact holes for exposing the upper surface of the plug patterns. Here, it is preferable that the diameter of the second buried contact holes is smaller than the top diameter of the first buried contact holes, i.e., the top diameter of the plug patterns, in consideration of mis-alignment between the second buried contact hole and the plug patterns. A conductive film such as a doped polysilicon film is formed on the entire surface of the resultant structure on which the second buried contact holes are formed. The conductive film is patterned to form a storage electrode covering the second buried contact holes.
According to another embodiment of the present invention, an interlayer insulating film and a first etch stop film are sequentially formed on a semiconductor substrate. Preferably, the interlayer insulating film is a planarized silicon oxide film, e.g., a film selected from the group consisting of doped silica glass and undoped silica glass. Alternatively, the interlayer insulating film is comprised of the doped silica glass and the undoped silica glass. First buried contact holes for exposing a predetermined region of the semiconductor substrate are formed by successively patterning the first etch stop film and the interlayer insulating film. A conductive film, e.g., a doped polysilicon film, for fil
Lee Kang-yoon
Park Jong-woo
Hiteshew Felisa
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tran Binh X.
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