Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-28
2003-09-30
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000
Reexamination Certificate
active
06627495
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a method for forming a capacitor in a semiconductor device, wherein the dielectric medium of the capacitor is a ferroelectric film or a high dielectric constant film.
DESCRIPTION OF RELATED ART
Ferroelectric material has come to be applied in semiconductor devices owing to its high dielectric constant and to its non-volatility and, thus, its ability to increase the density of DRAM (dynamic random access memory) and to form a new nonvolatile memory (FeRAM).
Typical ferroelectric materials include: Pb(Zr
x
Ti
x−1
)O
3
(“PZT”); (Sr,Bi)Ta
2
O
9
(“SBT”); SrBi
2
(Ta,Nb)
2
O
9
) (“SBTN”); and (Bi
x
La
y
)Ti
3
O
12
(“BLT”). For the upper and lower electrodes of the capacitor, metals such as platinum (Pt), iridium (Ir), ruthenium (Ru), and their alloys are used. In a ferroelectric capacitor, if a superior dielectric constant is to be obtained in the ferroelectric film, proper selection of the material for the upper and lower electrodes and proper control of the formation process are required.
Meanwhile, ferroelectric capacitors can be classified as an NPP structure and a plug poly (PP) structure. In the ferroelectric capacitor of the NPP structure, the upper electrode is connected through a metal wiring to the junction of a MOS transistor, so that the upper electrode can serve as a storage node, and the lower electrode can serve as a cell plate node.
On the other hand, in a ferroelectric capacitor of the PP structure, the lower electrode is connected through a polysilicon plug to the junction of a MOS transistor, so that the lower electrode can serve as a storage node, and the upper electrode can serve as a cell plate node.
In view of the density of the device, the ferroelectric capacitor of the PP structure preferably should be adopted rather than the ferroelectric capacitor of the NPP structure. However, if the PP structure is to be adopted, then a process difficulty is encountered.
That is, when forming the dielectric medium and the upper and lower electrodes, and when going through a high temperature thermal process such as the post-heat treatment, oxygen is diffused and, thus, a low dielectric constant silicon oxide film is formed upon the silicon oxide film (SiO
2
). In this case, externally supplied voltage is mostly imposed on the low dielectric constant silicon oxide film, with the result that a fatal defect is generated to hinder the operation of the device.
Meanwhile, the ferroelectric capacitor of the NPP structure is formed upon a silicon oxide film which is an interlayer insulating film. However, the metals or the alloys that are used for forming the lower electrode are very weak in the property of adhering to the silicon oxide film. Therefore, after going through the post thermal process, the lower electrode is peeled off, with the result that the yield of the device is greatly reduced.
In order to prevent this peeling phenomenon, usually there is inserted a TiO
x
film or a Ti film between the interlayer insulating film and the lower electrode.
In fabricating the above described ferroelectric capacitor of the NPP structure or the PP structure, the most fastidious process steps are the etching of the ferroelectric medium and the upper and lower electrodes.
That is, the ferroelectric film and the upper and lower electrodes cannot be etched chemically so that a physical etching process should be used to etch the ferroelectric film and the upper and lower electrodes.
In order to remove such a polymer, usually the photoresist is removed, and then a cleaning is carried out with a pure (de-ionized) water.
FIG. 1A
illustrates the particle distribution which is measured with a KLA apparatus after a cleaning with pure water.
FIG. 1B
graphically illustrates the number of the particles for different size classes as measured in FIG.
1
A.
In the case where cleaning is carried out with pure water, peeling of the capacitor pattern does not occur. However, the number of the detected particles is very high as shown in
FIGS. 1A and 1B
and, therefore, it is judged that cleaning with pure water is not effective at all in removing the organic polymer.
In order to solve the problems occurring when using the pure water in cleaning, it is proposed that EKC830 solution or ACT935 solution (amine-based organic solvents) be used.
FIG. 2A
illustrates the particle distribution measured with a KLA apparatus after carrying out cleaning with an organic solvent.
FIG. 2B
graphically illustrates the number of the particles for different size classes as measured in FIG.
2
A.
Referring to
FIGS. 2A and 2B
, in view of the fact that the number of the particles have been markedly decreased, it can be seen that most of the polymer has been removed. However, it is also seen that peeling of the capacitor pattern has occurred.
This peeling phenomenon is caused by the fact that the adhesive force between the lower electrode and the adhesive layer has been drastically weakened. Meanwhile, this adhesive layer is employed also in the PP structure, and therefore, the peeling phenomenon can occur even in the fabrication process for the PP structure capacitor. This problem can occur in the fabrication process for all the ferroelectric capacitors.
SUMMARY OF THE INVENTION
The invention is intended to overcome one or more of the above-described disadvantages of conventional techniques.
Therefore, it is an objective of the invention to provide a method for forming a capacitor in a semiconductor device, in which any peeling of the lower electrode is prevented, and the etch residues (organic polymer) formed during dry etching can be effectively removed.
In achieving this objective, a method for forming a capacitor in a semiconductor device according to the invention, with metal-based materials being used for upper and lower electrodes of the capacitor, includes the steps of: (a) carrying out a dry etch by using a photoresist pattern to expose a metal-based material on a substrate; (b) spreading an organic film upon the entire substrate after finishing the first step; and (c) carrying out a cleaning step to remove the organic film.
Preferably, after step (a), a step is carried out in which the photoresist pattern is removed.
Preferably, after step (b), a step is carried out in which a drying is carried out on the organic film.
Preferably, the organic film is polyhydroxystyrene, and in this case, at the third step, the polyhydroxystyrene and the photoresist pattern may be simultaneously removed.
Preferably, the drying is carried out at a temperature of 50° C. to 100° C. for 5 minutes to 20 minutes.
Preferably, in the case where the organic film is polyhydroxystyrene, the cleaning may be carried out with an MMP (methylmethoxypropionate) solution.
Preferably, the organic film is formed to a thickness of 1 &mgr;m to 10 &mgr;m.
REFERENCES:
patent: 6380574 (2002-04-01), Torii et al.
Cao Phat X.
Doan Theresa T.
Hynix / Semiconductor Inc.
Marshall Gerstein & Borun
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