Method for forming a capacitor in a mixed mode circuit...

Details Method for forming a capacitor in a mixed mode circuit... Method for forming a capacitor in a mixed mode circuit...

2002-04-09

2002-09-03

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S393000

Reexamination Certificate

active

06444519

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91106567, filed Apr. 2, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor fabrication. Particularly, the present invention relates to a method for forming a capacitor in a mixed mode circuit device using ion implantation.
2. Description of the Related Art
A mixed mode circuit device usually is that there are digital circuit device and analog circuit device formed on at the same logic region. The digital circuit device includes, for example, flip-flop circuit or adder and the analog circuit device includes, for example, amplifier, analog to digital converter and so on. In the mixed mode circuit device, it also usually includes capacitor, used for storing charges. Moreover, the charges stored in each the capacitor also need to remain the same.
FIGS. 1A-1C
are cross-sectional views, schematically illustrating a conventional fabrication processes for forming a capacitor in a mixed mode circuit device.
In
FIG. 1A
, the conventional method to form a capacitor in a mixed mode circuit device usually first forms a field oxide layer
102
on a substrate
100
. Then, a polysilicon layer
104
is formed on the field oxide layer
102
to serve as a lower electrode of the capacitor.
In
FIG. 1B
, a thermal oxidation process is performed to form an oxide layer
106
on the polysilicon layer
104
.
In
FIG. 1C
, another polysilicon layer
108
is formed on the oxide layer
106
. The polysilicon layer
108
and the oxide layer
106
are patterned to accomplish a capacitor.
The conventional method for forming capacitor usually takes a stack manner to form the capacitor of conductive-insulating-conductive structure. In this method, the necessary steps are high and complicate. Moreover, it is easy to cause defects on the interface for the capacitor formed by the stack manner, and further result in problems for the circuit.
SUMMARY OF THE INVENTION
The invention provides a method for forming a capacitor in a mixed mode circuit device through ion implantation, so as to reduce the complexity of fabrication processes and avoid defects on the interfaces.
The invention provides a method for forming a capacitor in a mixed mode circuit device through ion implantation. The method includes forming a polysilicon layer over a substrate, which substrate has isolation region formed thereon. An ion implantation process is performed to implant oxygen ions into the polysilicon layer. An annealing process is performed to trigger an reaction between the oxygen ions and the silicon ions. As a result, a silicon oxide layer is formed within the polysilicon layer. The silicon layer and the polysilicon layer are patterned, where the top portion of the polysilicon layer above the silicon oxide layer serves as an upper electrode of a capacitor. The polysilicon layer below the silicon oxide layer serves as the lower electrode. The capacitor in a mixed mode circuit device is accomplished.
In the invention, since the ion implantation is used to implant oxygen ions into the polysilicon layer. After the annealing process, the oxide layer is formed with the polysilicon layer. The fabrication processes are simplified. Moreover, the oxide layer within the polysilicon layer is formed gradually, so that the defect on the interface is effectively avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5217908 (1993-06-01), Nakanishi
patent: 5250456 (1993-10-01), Bryant
patent: 6124161 (2000-09-01), Chern et al.
patent: 2001/0019874 (2001-09-01), Uemoto
patent: 2002/0061604 (2002-05-01), Sitaram et al.

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