Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-22
2001-02-27
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S964000
Reexamination Certificate
active
06194266
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a capacitor for dynamic random access memory (DRAM) device, and more particularly, a method for forming selective hemispherical grained polysilicon of the capacitor.
2. Description of the Prior Art
The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for capacitors having increased capacitance and reduced feature widths.
With respect to dynamic memory devices, storage node capacitor cell plates must be sufficiently large to retain an adequate charge. This is particularly significant when taking device noise and parasitic effects into account. As density of semiconductor devices, such as DRAM arrays, has continued to increase with industry trends, the issue of maintaining storage node capacitance has grown in importance.
In light of the above demands, several techniques have been proposed to increase the capacitance of capacitors without effecting the cell area. These techniques have included utilizing trench and stacked capacitor structures, as well as new dielectric material having increased dielectric constants
Another approach for increasing capacitance while reducing feature size known in the art is the formation of roughened polysilicon film, such as hemispherical grained (HSG) polysilicon, as a capacitor storage node. Fundamentally, by relying on roughened polysilicon, a larger surface area is formed for the same planar area that is available for the capacitor. Given the advantages of enhanced capacitance, selective hemispherical grained (S-HSG) polysilicon has been widely employed in storage node processing of DRAM fabrication. This S-HSG structure is utilized to increase surface areas of lower electrode plate (usually polysilicon) so that the electrode layout can be shrunk as well as the whole chip size.
Formation of an S-HSG node typically includes S-HSG growth, in-diffusion (annealing), and dielectric (e.g. ONO, oxide-nitride-oxide) depositions. Cleaning in-between the main process steps is additionally applied as required. However, since S-HSG is quite sensitive to cleaning procedures, defects are easily made during such treatments, and thus influence electrical yield of the product. One solution known to minimize the defects is the adaptation of so-called in-situ (performed HSG process without leaving the same chamber) fabrication.
In case in-situ (one-chamber) process was not accessible by the existing facilities, conventional multi-furnaces (ex-situ process) would be used. The ex-situ S-HSG process normally includes some wet cleaning steps (e.g. DHF, dilute hydrofluoric acid, process) for post-treating of the amorphous S-HSG before the dopant in-diffusion step. The wet clean herein is mainly to remove native oxide on the S-HSG silicon layer. Besides, it serves to make subsequent dopant in-diffusion efficient while attaining flowing silicon surface migration and enlarging surface area of the S-HSG. However, this wet cleaning has several shortcomings. One particular failing is the necking of the grains (e.g. grain
101
), as indicated in
FIG. 1
, due to excess silicon migration of the HSG. The cleaning also weakens the connections of the HSG (grains
102
and
103
) to polysilicon
105
and causes some small grain particles (such as
102
in the figure) to depart from the silicon
105
surface. In addition, applications of the wet treatment often result in over-etching of the oxide layer
107
underneath the polysilicon nodes, and form defective portions, such as the one (
109
) indicated in the figure, of the structure. Severe defects of the kind could endanger the connections of the poly nodes to the oxide substrate. Furthermore, electrical shortage between adjacent nodes occasionally occurred during mass production of the product. Such occurrence is strongly related to the tiny residues left after the cleaning.
As such, there is a need for a method to reduce defect generations from the wet cleaning during ex-situ S-HSG process. The present invention suggests one to minimize opportunities of defect formation while still keeping up good capacitance level of the structure.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating a capacitor with ex-situ formed selective hemispherical grained (S-HSG) polysilicon. In one embodiment, an undoped storage node electrode with a roughened amorphous selective hemispherical grained (S-HSG) polysilicon layer is formed on an insulting layer (the insulting layer is a part of a semiconductor substrate). Phosphine annealing is then applied to the structure for dopant in-diffusion of the S-HSG, followed by dopant (n-type) implantation of the S-HSG. However, the doping sequence can be switched. In another embodiment, the implantation would be proceeded prior to the in-diffusion process. After the doping procedure, the structure is treated with wet cleaning. Then a layer of capacitor dielectric and next a polysilicon layer is formed to conclude the construction of the capacitor.
In this invention, dopant implantation is incorporated after the S-HSG growth to replace the wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.
REFERENCES:
patent: 5639685 (1997-06-01), Zahurak et al.
patent: 5877052 (1999-03-01), Lin et al.
patent: 5897352 (1999-04-01), Lin et al.
patent: 5943584 (1999-08-01), Shim et al.
patent: 5963804 (1999-10-01), Figura et al.
patent: 6066529 (2000-05-01), Lin et al.
Chen Terry Chung-Yi
Hsia Da-Wen
Huang Cheng-Chieh
Kung Cheng-Chih
Chen Jack
Nguyen Tuan H.
United Microelectronics Corp.
LandOfFree
Method for forming a capacitor having selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a capacitor having selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a capacitor having selective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2578224