Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-23
2001-08-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S240000, C438S393000
Reexamination Certificate
active
06274424
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to, forming oxygen-tolerant inlaid plugs for use in memory.
BACKGROUND OF THE INVENTION
The integrated circuit (IC) industry is attempting to create integrated circuits (ICs) having embedded-DRAM on-chip with metal-oxide-semiconductor (MOS) logic circuitry. However, conventional CMOS logic processing, which uses tungsten (W) and/or polysilicon conductive plugs, is not readily integratable with ferroelectric embedded DRAM processing. Specifically, ferroelectric materials require an oxygen anneal process and/or an oxygen environment deposition process in order to improve the dielectric properties of the ferroelectric capacitor. This deposition or anneal process can adversely oxidize underlying/exposed tungsten and polysilicon plugs which are formed as contacts to MOS DRAM and logic transistors. Due to this oxidation problem, additional processing steps and structures are added to the process flow in an attempt to avoid this adverse plug oxidation.
Furthermore, lower capacitor electrodes of embedded DRAM capacitors are typically reactive ion etched (RIE) resulting in the formation of reactive ion-etched bottom capacitor electrode sidewalls. The reactive ion etch (RIE) of this bottom capacitor electrode roughens the surface of these sidewalls, thereby creating unwanted leakage current in the capacitor device between these sidewalls and an overlying capacitor electrode. A need exists in the IC industry to reduce or eliminate both the plug oxidation problem and the sidewall leakage current problem associated with embedded ferroelectric DRAM technology.
Specifically, the two problems discussed above (i.e., plug oxidation and sidewall capacitor current leakage) are graphically illustrated in the prior art FIG.
1
.
FIG. 1
illustrates tungsten plugs or polysilicon plug regions
214
as illustrated in FIG.
1
. These plugs are formed to a minimum lithographic dimension W
1
(roughly 0.25 microns by current standards). However, any exposed portions of the tungsten (W) or polysilicon plug
214
will be readily oxidized in an oxidation environment. In an attempt to prevent plug oxidation, an oxidation barrier layer
215
is formed overlying the contact plug
214
As illustrates that the barrier layer
215
surrounds a periphery of the contact plug by dimension W
2
. The ferroelectric layer
218
is annealed, or oxygen-environment deposited, to improve the dielectric properties of the ferroelectric material. The oxygen atoms in this temperature-elevated environment may diffuse through the ferroelectric layer
218
and may traverse the distance W
2
in layers
215
/
212
to oxidize the plug
214
. As the lithographic feature size W
1
and cell size of the DRAM cell of
FIG. 1
continues to shrink over time, this dimension W
2
will also reduce in size. In addition, the distance W
2
can be reduced by lithographic misalignment which is present in all lithographic processing. If the dimension W
2
, through lithographic misalignment or through cell shrinkage, becomes less than a threshold value, oxygen will be able to readily diffuse through the distance W
2
and begin to oxidize upper comers of the tungsten (W) or polysilicon plug
214
. This oxidation adversely effects contact resistance of the plug
214
and also adds parasitic interfacial capacitance to the DRAM storage node which compromises the operation of the DRAM cell.
A top capacitor electrode
220
is then formed, after oxygen annealing of layer
218
, and lithographically patterned and etched along with the capacitor dielectric
218
as illustrated in FIG.
1
. Note that
FIG. 1
illustrates a bottom electrode sidewall
219
. This sidewall
219
has been created by reactive ion etching (RIE) of the lower capacitor electrode whereby this sidewall
219
has been roughened by the reactive ion etch (RIE) process. Due to the presence of this rough sidewall surface
219
in the capacitor structure, unwanted leakage current will occur between the sidewall
219
and the upper electrode
220
. It would be advantageous to reduce or eliminate this sidewall leakage current effect.
Therefore, a need exists in the industry for an embedded DRAM capacitor cell which: (1) prevents the formation of parasitic interfacial capacitance and prevents increased plug contact resistance by avoiding or reducing unwanted plug oxidation; and (2) reduces sidewall leakage current due to RIE etching of a bottom capacitor electrode.
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Netter et al., “Oxidation Resistant Coatings Produces By Chemical Vapor Deposition: Iridium and Aluminum Oxynitride Coating”, 1990 MRS, vol. 168,pp. 247-252.*
P. Netter et al., “Oxidation Resistant Coatings Produced By Chemical Vapor Deposition: Iridium and Aluminum Oxynitride Coatings”, Mat. Res. Soc. Symp. Proc., vol. 168, 1990, pp. 247-252.
K.N. Kim et al., “Highly Manufacturable 1Gb SDRAM”, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 9-10.
Y. Kohyama et al., “A Fully Printable, Self-Aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond”, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 17-18.
Jones, Jr. Robert Edwin
White, Jr. Bruce E.
Bowers Charles
Huynh Yennhu B.
Meyer George R.
Motorola Inc.
Rodriguez Robert A.
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