Method for forming a buried digit line with self aligning...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S396000, C257SE21646

Reexamination Certificate

active

07364966

ABSTRACT:
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

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J.M. Hergenrother et al, “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length”, Bell Laboratories, Lucent Technologies 0-7803-5413 1999 IEEE.
Copending US application: “Semiconductor Structures, and Methods of Forming Semiconductor Constructions,” Terrence B. McDaniel et al., filed Apr. 6, 2005, U.S. Appl. No. 11/099,972.

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