Method for forming a bottom polysilicon electrode of a stacked c

Details Method for forming a bottom polysilicon electrode of a stacked c Method for forming a bottom polysilicon electrode of a stacked c

1996-02-20

2000-05-16

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

498398, H01L 218242

Patent

active

060636610

ABSTRACT:
A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAMs makes use of a double-layered polysilicon structure and a phosphoric acid etching. When the double-layered polysilicon structure is etched with the phosphoric acid, the polysilicon grain boundary is etched at a rate faster than the polysilicon grain itself so as to enable the formation of a rugged surface and thus increases the total surface area.

REFERENCES:
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5286668 (1994-02-01), Chou
patent: 5597755 (1997-01-01), Ajika et al.
H. Watanabe et al., "Device application and structure observation for hemispherical-grained Si," J. Appl. Phys. 71(7), Apr. 1, 1992, pp. 3538-3543.
M. Yoshimaru et al., "Rugged surface poly-Si electrode and low temperature deposited Si.sub.3 N.sub.4 for 64Mbit and beyond STC DRAM cell," 1990 IEEE IEDM, pp. 659-662.
H. Watanabe et al., "A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256Mb DRAMs," 1992 IEEE IEDM, pp. 259-262.
H. Watanabe et al., "A novel capacitor with porous-Si electrodes for high density DRAMs," Symposium on VLSI Technology, 1993, pp. 17-18.

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