Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-08
2007-05-08
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S680000, C257SE21170, C257SE21169
Reexamination Certificate
active
11052010
ABSTRACT:
A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma is maintained at the target to produce a stream of principally neutral atoms flowing from the target toward the wafer for vapor deposition. A wafer-sputtering plasma is maintained near the wafer support pedestal to produce a stream of sputtering ions toward the wafer support pedestal for re-sputtering. The sputtering ions are accelerated across a plasma sheath at the wafer in a direction normal to a surface of the wafer to render the sputter etching highly selective for horizontal surfaces.
REFERENCES:
patent: 3461054 (1969-08-01), Vratney
patent: 4539068 (1985-09-01), Takagi et al.
patent: 4837185 (1989-06-01), Yau et al.
patent: 4963239 (1990-10-01), Shimamura et al.
patent: 4999096 (1991-03-01), Nihei et al.
patent: 5308793 (1994-05-01), Taguchi et al.
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5507930 (1996-04-01), Yamashita et al.
patent: 5510011 (1996-04-01), Okamura et al.
patent: 5656123 (1997-08-01), Salimian et al.
patent: 5933753 (1999-08-01), Simon et al.
patent: 5933973 (1999-08-01), Fenley, Jr.
patent: 5976327 (1999-11-01), Tanaka
patent: 5986762 (1999-11-01), Challener
patent: 6051114 (2000-04-01), Yao et al.
patent: 6080285 (2000-06-01), Liu et al.
patent: 6197167 (2001-03-01), Tanaka
patent: 6216632 (2001-04-01), Wickramanayaka
patent: 6228236 (2001-05-01), Rosenstein et al.
patent: 6251242 (2001-06-01), Fu et al.
patent: 6274008 (2001-08-01), Gopalraja et al.
patent: 6277249 (2001-08-01), Gopalraja et al.
patent: 6287977 (2001-09-01), Hashim et al.
patent: 6309978 (2001-10-01), Donohoe et al.
patent: 6350353 (2002-02-01), Gopalraja et al.
patent: 6352620 (2002-03-01), Yu et al.
patent: 6377060 (2002-04-01), Burkhart et al.
patent: 6436251 (2002-08-01), Gopalraja et al.
patent: 6444104 (2002-09-01), Gopalraja et al.
patent: 6444137 (2002-09-01), Collins et al.
patent: 6451177 (2002-09-01), Gopalraja et al.
patent: 6462482 (2002-10-01), Wickramanayaka et al.
patent: 6485617 (2002-11-01), Fu et al.
patent: 6485618 (2002-11-01), Gopalraja et al.
patent: 6488807 (2002-12-01), Collins et al.
patent: 6498091 (2002-12-01), Chen et al.
patent: 6518195 (2003-02-01), Collins et al.
patent: 6545420 (2003-04-01), Collins et al.
patent: 6554979 (2003-04-01), Stimson
patent: 6559061 (2003-05-01), Hashim et al.
patent: 6652718 (2003-11-01), D'Couto et al.
patent: 6660622 (2003-12-01), Chen et al.
patent: 6709987 (2004-03-01), Hashim et al.
patent: 6755945 (2004-06-01), Yasar et al.
patent: 6787006 (2004-09-01), Gopalraja et al.
patent: 2001/0023822 (2001-09-01), Koizumi et al.
patent: 2001/0050220 (2001-12-01), Chiang et al.
patent: 2002/0004309 (2002-01-01), Collins et al.
patent: 2002/0104751 (2002-08-01), Drewery et al.
patent: 2003/0116427 (2003-06-01), Ding et al.
patent: 2004/0025791 (2004-02-01), Chen et al.
patent: 2004/0188239 (2004-09-01), Robison et al.
patent: 2006/0073283 (2006-04-01), Brown et al.
patent: 2006/0073690 (2006-04-01), Brown et al.
patent: 0782172 (1997-07-01), None
patent: 0799903 (1997-10-01), None
patent: 0807954 (1997-11-01), None
patent: 0841683 (1998-05-01), None
patent: 0878825 (1998-11-01), None
patent: 1094493 (2001-04-01), None
patent: 1128414 (2001-08-01), None
patent: 1146543 (2001-10-01), None
U.S. Appl. No. 10/693,775, filed Oct. 25, 2003 entitled Tantalum Barrier Layer for Copper Metallization by Ling Chen, et al.
U.S. Appl. No. 10/761,466, filed Jan. 21, 2004 entitled Method and Apparatus for Forming Improved Metal Interconnects by Imran Hashim, et al.
U.S. Appl. No. 10/934,231, filed Sep. 3, 2004 entitled Multi-Step Magnetron Sputtering Process by Praburam Gopalraja, et al.
Wickramanayaka, S., et al., “Using I-PVD for copper-based interconnects,”Solid State Technology, Oct. 2002, pp. 67-74.
Boyle, P.C., et al., “Independent control of ion current and ion impact energy onto electrodes in dual frequency plasma devices”,Journal of Physics D: Applied Physics, 2004, pp. 697-701, vol. 37, Institute of Physics Publishing, United Kingdom.
Brown Karl M.
Mehta Vineet
Pipitone John
Applied Materials Inc.
Nhu David
Wallace Robert M.
LandOfFree
Method for forming a barrier layer in an integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a barrier layer in an integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a barrier layer in an integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3802389