Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-04-14
2001-02-13
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S624000, C438S626000, C438S692000, C438S712000, C438S788000
Reexamination Certificate
active
06187683
ABSTRACT:
RELATED APPLICATIONS
The following application is related to the present application and is incorporated herein by reference: European application no. 97830174.5.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for protecting semiconductor integrated circuits against mechanical stress or chemical agents and, more particularly, to methods for forming a passivation layer on such circuits to provide such protection.
2. Discussion of the Related Art
Semiconductor integrated circuits (hereafter referred to as chips) manufactured with Large Scale Integration technologies (LSI, VLSI, ULSI, and the like) typically are covered by a protective layer to protect against mechanical stress and aggressive chemical agents. This protective layer, referred to herein as the final passivation layer, typically is formed of silicon-based dielectric materials, such as silicon dioxide (USG), phosphorus-doped or fluorurate-doped silicon oxide (PSG or FSG), silicon nitrides and nitride oxides (SiOxNy, Si3N4).
The final passivation layer is conventionally formed by use of Chemical Vapor Deposition (CVD) techniques, either the plasma-enhanced CVD technique (PECVD) or the atmospheric pressure CVD technique (APCVD). The top surface of the final passivation layer formed by conventional techniques generally is not planar, having protrusions and depressions caused by gaps in the underlying layers (for example, gaps between metal lines of the uppermost metal interconnection layer). Such a non-planar top surface is disadvantageous because, when the chip is encapsulated in a package, the mechanical stress exerted by the package on the chip generally is not uniformly distributed over the top surface of the final passivation layer. Such non-uniform distribution of stress can lead to cracks in the final passivation layer, through which chemical agents or water molecules can penetrate and reach the underlying layers of the chip.
Therefore, what is needed is a method for protecting chips against such cracking due to non-uniform distribution of stress over the top surface of the final passivation layer.
SUMMARY OF THE INVENTION
According to the present invention, the aforementioned need is met by a process of final passivation, including planarization, of an integrated circuit device including at least one chip. Such process includes the steps of forming a final passivation layer over a top surface of the integrated circuit, and planarizing (that is, making substantially flat) the final passivation layer to obtain a substantially flat (hereafter, planar) top surface thereof.
Preferably, the planarizing step is performed by use of a Chemical Mechanical Polishing (CMP) technique. CMP is a technique already known in the field of integrated circuit manufacturing, where it is used to planarize inter-metal dielectric layers (i.e., dielectric layers provided between superimposed metal layers to electrically isolate one from the other). Alternatively, the planarizing step may be performed in accordance with a Reactive Ion Etching (RIE) technique, which is another technique already employed in the field of integrated circuit manufacturing for selectively removing layers of material.
The step of forming the final passivation layer in accordance with the present invention advantageously includes a conventional chemical vapor deposition of a suitable material, as described below, either by plasma-enhanced CVD or CVD at atmospheric pressure. In a preferred embodiment of the invention, the formation of the final passivation layer is performed in accordance with the so-called High-Density Plasma CVD (HDPCVD) technique, a known deposition technique for the formation of inter-metal dielectric layers in integrated circuits of very small geometries. The use of HDPCVD for forming the final passivation layer allows for a better filling of gaps in the underlying layers.
The planarizing step is particularly advantageous in the case of multichip devices, i.e., devices including two or more distinct chips encapsulated in the same package. In accordance with conventional techniques, not only does the final passivation layer of each chip typically have depressions and protrusions, but the top surfaces of the final passivation layers of the different chips generally are at different heights, due to the fact that each chip generally has a different thickness from the others. The present invention, which includes a planarizing step applied to the final passivation layer covering the multichip device, provides that the top surfaces of the final passivation layers of the different chips are at the same height.
Advantageously, such planarization of the final passivation layer, both with respect to single chips and multiple chips, generally increases the uniformity of mechanical stresses typically imposed by the packaging on the top surface of the final passivation layer, as compared to imposition of such stresses on final passivation layers that have not been so planarized. Such uniformity of stresses generally reduces cracks in the final passivation layer that may act as sites for penetration by chemical agents, water molecules, or other substances.
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Crisenza Giuseppe
De Santi Giorgio
Zanotti Luca
Galanthay Theodore E.
Guerrero Maria
Jr. Carl Whitehead
Morris James H.
SGS--Thomson Microelectronics S.r.l.
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