Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-04-29
2004-02-17
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S618000, C438S637000, C438S760000, C438S778000, C438S781000, C438S782000
Reexamination Certificate
active
06693049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for filling a fine hole(s), being less than or equal to 0.18 p &mgr;m in the hole pattern diameter, in a case of forming a multilayered wiring structure.
2. Description of Prior Art
FIGS.
1
(
a
) to
1
(
i
) show one example of processes for forming a multilayered wiring structure. In the conventional method for forming such a multilayered wiring structure, first of all, as shown in FIG.
1
(
a
), an aluminum (Al) film is formed on a substrate, on which selectively etched through RIE (Reactive Ion Etching) and the resist mask is removed, as shown in FIG.
1
(
b
), thereby a lower-layer wiring is formed. Next, as shown in FIG.
1
(
c
), SOG (Spin On Glass: a coating liquid obtained by dissolving a silicon compound into an organic solvent such as alcohol) is applied and baked. Although the SOG layer is provided directly on the Al wiring in FIG.
1
(
c
), an insulation layer may be provided between the Al wiring and the SOG layer through a plasma CVD method if necessary. Next, as shown in FIG.
1
(
d
), the surface is flattened by etching-back, and, as shown in FIG.
1
(
e
), SOG is applied on the flattened surface and baked. Through a resist mask provided thereon, as shown in FIG.
1
(
f
), so-called via-holes are formed in this SOG film by selective etching, and Al or the like is embedded in the via-holes. Further, as shown in FIG.
1
(
g
), an aluminum (Al) film is formed, and, as shown in FIG.
1
(
h
), it is etched and thereby an upper layer wiring is formed in the same manner as mentioned above. And, as shown in FIG.
1
(
i
), SOG is applied so as to fill spaces between the upper layer wiring with the SOG, and thereby a multilayered wiring structure is formed. In many of the multilayered wiring structures, five (5) layers are built up in the actual structure by applying such etching technology as mentioned above.
Requirements for high integration of semiconductor devices are increasing more and more, and at present, the new generation of gate length is 0.15 a &mgr;m. As a material for the wiring in such a case, it is already known that the characteristics of the semiconductor device can be improved by using copper (Cu) in place of aluminum (Al) used conventionally in the following aspects.
Cu is superior to Al the durability against EM (Electro Migration), and because of a low resistance thereof, it is possible to reduce the signal delay due to the resistance of wiring. Also, it is possible to apply a high current density thereto, i.e., it can increase the allowable current density by three (3) times or more, and thereby miniaturization in the width of the wiring is achieved.
However, since Cu is a difficult material to be etched compared to Al, more attention is paid on a damascene method as one through which the multilayered wiring structure of Cu can be obtained without etching of Cu.
Explanations will be made on the damascene method, in particular, a copper damascene method, by referring to FIGS.
2
(
a
) to
2
(
g
). First, as shown in FIG.
2
(
a
), an inter-layer insulation film of SiO
2
, SOG, or the like is formed on a substrate using a CVD method, a patterned resist mask is provided on this, and wiring grooves are formed by selective etching and removal of the resist mask, as shown in FIG.
2
(
b
). Next, as shown in FIG.
2
(
c
), barrier metal is accumulated, and as shown in FIG.
2
(
d
), Cu is embedded in the grooves through electroplating or the like so as to form a lower-layer wiring. Next, polishing is conducted upon the barrier metal and the Cu by a CMP (Chemical polishing) method, and thereafter, as shown in FIG.
2
(
e
), another inter-layer insulation film is formed on it. Hereinafter, in the same manner, by selective etching of the inter-layer insulation film through a patterned resist mask, via-holes (contact holes) and trench holes (grooves for an upper-layer wiring) are formed (dual-damascene), as shown in FIG.
2
(
f
). Next, as shown in FIG.
2
(
g
), Cu is embedded in the via-holes and the grooves for an upper-layer wiring through electroplating or the like so as to form an upper-layer wiring.
Such a dual-damascene method for forming via-holes and trench holes in inter-layer insulation films is disclosed in, for example, a monthly magazine (“Semiconductor World”, 1998.1, pages 108-109). Hereinafter, examples of such processes will be explained by referring to FIGS.
3
(
a
) to
4
(
g
).
In a method shown in FIGS.
3
(
a
) to
3
(
g
), first as shown in FIG.
3
(
a
), on a semiconductor substrate are formed a first low-k dielectric film and a second low-k dielectric film sequentially. Next, as shown in FIG.
3
(
b
), on the second low-k dielectric film is formed a resist mask having a pattern therein for forming via-holes. Next, as shown in FIG.
3
(
c
), through this resist mask, via-holes are formed through the first low-k dielectric film. As shown in FIG.
3
(
d
), filler such as photo-resist or the like is filled into the via-holes, heated and cured. Next, as shown in FIG.
3
(
e
), the filler cured by heating is etched back, so that the filler remains in the bottom of the via-holes with predetermined thickness. Further, as shown in FIG.
3
(
f
), on the second low-k dielectric film is formed a resist mask having a pattern therein for forming trench holes. As shown in FIG.
3
(
g
), through this resist mask, trench holes are formed in the second low-k dielectric film, while the filler remaining in the bottom of the via-holes is removed at the same time. Next, metal such as copper or the like is embedded in the trench holes and the via-holes (not shown). In this connection, it has been proposed that an etching stopper film (not shown) is provided between layers or between the substrate and the low-k dielectric film.
In a method shown in FIGS.
4
(
a
) to
4
(
g
), first of all, as shown in FIG.
4
(
a
), on the semiconductor substrate is formed a low-k dielectric film. Next, as shown in FIG.
4
(
b
), on the low dielectric film is formed a resist mask having a pattern therein for forming via-holes. Next, as shown in FIG.
4
(
c
), through this resist mask, via-holes are formed in the low-k dielectric film. As shown in FIG.
4
(
d
), filler such as photo-resist is filled into the via-holes, heated and cured. Further, as shown in FIG.
4
(
e
), on the low-k dielectric film is formed a resist mask having a pattern therein for forming trench holes. As shown in FIG.
4
(
f
), trench holes are formed in the low-k dielectric film through the resist mask, while the filler remaining in the bottom of the via-holes is removed. Next, metal is embedded in the trench holes and the via-holes. Also filler having a predetermined thickness may be filled into the bottom of the via-holes without an etching back process as shown in FIGS.
5
(
a
)-
5
(
f
).
In addition to the dual-damascene method described above, there is also known another such method wherein trench holes are formed in advance and thereafter via-holes are formed without using filler such as photo-resist.
However, in the dual-damascene method mentioned above, when the trench holes are formed through an etching process after formation of the via-holes, if the surface of the substrate is exposed in the bottom of the via-hole, the surface of the substrate is damaged by the etching gas, and thereby defects in the wiring are caused. Therefore, a photo-resist composition is filled into the bottom of the via-hole as a protection film.
However, in a case where a hole pattern diameter of holes formed by the dual-damascene method is less than or equal to 0.18 &mgr;m, the filler is required to be such a material that can be easily filled into such fine holes.
However, even if a conventional photo-resist composition is filled into such fine holes having a hole pattern diameter of less than or equal to 0.18 &mgr;m, bubbles generated in the photo-resist composition prevent the photo-resist composition from being perfectly filled and the function of a protection film cannot be obtained. Also, in a case of using the p
Iguchi Etsuko
Tanaka Takeshi
Blackman William D.
Carrier Joseph P.
Carrier Blackman & Associates P.C.
Lebentritt Michael S.
Owens Beth E.
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