Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-29
2001-05-29
Ngô ;, Ngâ ;n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S351000
Reexamination Certificate
active
06239469
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of silicon on insulator technology; and, more particularly, it relates to a method for fabricating silicon on insulator regions on a silicon wafer.
BACKGROUND OF THE INVENTION
Silicon on insulator (SOI) technology offers many advantages over conventional bulk silicon technology. Among these is the ability to build high performance, high speed, low power complementary-metal-oxide-semiconductor (CMOS) devices.
Turning to the prior art, one well known method to produce a silicon on insulator substrate is by bonding together two silicon wafers, each having an oxide layer, in a high temperature furnace step. Usually one side of the fused wafer needs to be thinned by chemical-mechanical-polishing. Another well known method is SIMOX (Separation by Implanted Oxygen) technology. In this technique a high dose oxygen ion implantation step is performed to place oxygen atoms in the silicon wafer at a fixed distance from the surface. This is followed by an anneal step, which then forms the buried oxide layer. Both these processes produce whole wafer silicon on insulator wafers.
Other techniques for fabricating silicon on insulator substrates use etch and oxidation steps to produce isolated silicon islands in a silicon substrate. For example, U.S. Pat. No. 5,185,286 to Eguchi, describes a process for producing a laminated semiconductor comprising the steps of forming openings in an oxide film on a silicon wafer, forming a silicon nitride island midway between the openings, growing epitaxial silicon, polishing to produce a flat surface, and selectively oxidizing the epitaxial silicon over the original openings in the oxide layer. One concern with this method is that the silicon island which is produced is located between a block of silicon nitride and an area of thermally oxidized silicon, subjecting the island to stresses.
U.S. Pat. No. 5,321,298 to Moslehi, describes a method for forming a semiconductor on insulator wafer with a single crystal semiconductor substrate comprising the steps of etching trenches in the substrate, forming oxide on the bottom of the trenches, growing epitaxial silicon to partially fill the trenches, forming a nitride spacer on top of the trenches, growing a second epitaxial silicon to fill the trenches, removing the nitride spacer, etching the epitaxial silicon down to the oxide originally formed at the bottom of the trenches and then filling the new trenches with oxide. Drawbacks with this method are its complexity and the integrity of the silicon crystal structure grown on many epitaxial fronts.
U.S. Pat. No. 5,691,230 describes a method of forming silicon on insulator rows and islands in a silicon substrate. Trenches are directionally etched in the silicon substrate. The tops of the rows and bottoms of the trenches are coated with silicon nitride. An isotropic etch is used to partially undercut the silicon rows. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. This method leaves a topology that may be disadvantageous to fabrication of high density circuits.
The present invention is directed toward a method of fabricating silicon on insulator regions on a substrate that produces silicon islands that are of good crystal integrity, low stress and coplanar with the rest of the wafer surface, while easily fabricated.
SUMMARY OF THE INVENTION
The invention provides a method for forming regions of silicon on insulator in bulk silicon wafers. A trench or recess is first formed in the bulk silicon wafer by a first etch process, and it is then filled in with a first dielectric. After a chemical-mechanical-polish step to planarize the surface, dielectric filled trenches or islands are left surrounded by bulk silicon. At this point either polysilicon is deposited and a re-crystallization step performed or epitaxial silicon is grown directly using the exposed bulk silicon as a seed layer. This produces a single crystal silicon layer extending over the dielectric filled trenches or islands. A second silicon etch process is performed to remove all the single crystal silicon except in regions directly over the now buried first dielectric. Care is taken to ensure a lip or peripheral region of first dielectric is left exposed all around the remaining single crystal silicon. The trenches formed by this second etch are then filled with a second dielectric. The second dielectric contacts the lip left exposed on the first dielectric. Therefore, after a chemical-mechanical-polish step, islands of single crystal silicon have been formed which are isolated from each other and the bulk silicon wafer.
A particular advantage of the invention is that it is suitable as a pre-fabrication process on dies where both bulk and silicon on insulator devices are to be fabricated, especially if identical CMOS devices are fabricated simultaneously in both the bulk and the silicon on insulator portions of the die. Therefore, it is an object of the present invention to provide a method suitable for both fabricating silicon on insulator wafers and bulk silicon wafers having silicon on insulator regions.
The method of forming the single crystal silicon layer described above can leave a seam of mismatched crystal planes and non-perfect crystal structure where the growth edges meet. When the size of the single crystal islands are large enough for many devices to be fabricated, the seam region in the single crystal silicon in each island can be avoided. For example, gates would not be placed in these regions. However, if it is desirable to isolate individual devices in very small silicon islands, the silicon islands should be fabricated larger than required initially, and then subdivided along the seam boundaries. This may be accomplished by etching a trench in each of the silicon islands along the seam boundary and backfilling with a third dielectric fill. Therefore, it is a further object of the present invention to provide a method suitable for silicon on insulator regions having high quality crystal structure.
REFERENCES:
patent: 5185286 (1993-02-01), Eguchi
patent: 5321298 (1994-06-01), Moslehi
patent: 5691230 (1997-11-01), Forbes
patent: 6064092 (2000-05-01), Park
patent: 6147384 (2000-11-01), Chen
Bolam Ronald Jay
Evans Richard James
Palagonia Anthony Michael
International Business Machines - Corporation
Ngô ; Ngâ ;n V.
Sabo William D.
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