Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2001-03-28
2002-12-17
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S787000
Reexamination Certificate
active
06495475
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a method of forming a dielectric composite, and more particularly to a method of forming a silicon nitride film of an ONO composite for use as an interpoly dielectric.
BACKGROUND ART
Interpoly dielectric structures comprising an ONO dielectric structure having silicon dioxide/silicon nitride/silicon dioxide layers are known in the art. ONO dielectrics are used in the fabrication of non-volatile memory devices such as EPROM, EEPROM, and FLASH and other capacitor devices.
As is known in the prior art, in general, nonvolatile memory devices comprise a series of memory cells. Each memory cell includes source and drain regions formed on the surface of a substrate, an insulating layer positioned between the source and drain regions, a floating gate on the insulating layer, a layer of insulating dielectric on the floating gate and a control gate on the insulating dielectric. The floating gate holds a charge and the insulating dielectric insulates the floating gate and assists it in maintaining its charge. A bit of binary data is stored in the floating gate. The value of the data is a function of the charge, therefore charge loss or gain can alter the value of the data. It is essential that each floating gate is capable of long-term charge retention.
The ability of a floating gate to retain its charge is primarily determined by the dielectric material used to insulate the floating gate. To prevent charge loss the dielectric must have a sufficiently high break down voltage to block electrons from the floating gate to the control gate when a high voltage potential is applied to the control gate during programming. Energy expended to introduce a charge into a floating gate is a function of the capacity between the floating gate and the control gate and is related to the thickness of the dielectric layer. Because capacitance is directly proportional to the dielectric constant and the surface area of the dielectric layer, increasing the surface area or decreasing the thickness of the dielectric layer will increase the capacitance of a memory cell. As the density of devices employing memory cells becomes smaller, the area that each device occupies becomes smaller. The resulting smaller devices are characterized by a lower capacitance. Therefore it is desirable to minimize the thickness of the insulating dielectric layer in order to minimize the energy needed to pass a charge in and out of a floating gate and to increase the device capacitance.
ONO dielectric composites have a silicon dioxide layer, a middle layer composed of silicon nitride covering the silicon dioxide layer and a layer of silicon dioxide covering the silicon nitride layer. Oxidation of the silicon nitride layer of an ONO composite thins the silicon nitride layer, thus minimizing the thickness of the insulating dielectric. U.S. Pat. No. 5,619,052 to Chang et al. provides during processing steps, such as oxidation of the nitride layer, the nitride layer should be made to be thinner than either oxide layer.
U.S. Pat. No. 5,504,021 to Hong et al. describes a method for fabricating an ONO stacked dielectric. The method involves depositing a thin nitride layer of a thickness of approximately 20 to 60 angstroms on the surface of a silicon substrate. The nitride layer is oxidized using a low-pressure dry-oxidation procedure to form the ONO stacked dielectric.
Unfortunately, as the thickness of the dielectric is reduced, charge leakage through pinholes and other defects present in the dielectric generally increases.
U.S. Pat. No. 5,882,978 to Srinivasan et al. provides a method for decreasing defects within the silicon nitride layer of a capacitor dielectric. The process involves forming a first layer of silicon nitride over a substrate. The silicon nitride has an outer surface having pinholes formed therein. The pinholes are widened with preferably a wet acid etching solution (for example phosphoric acid). A second layer comprising silicon is formed on the first layer and within the widened pinholes. The silicon of the second layer is nitridized into silicon nitride to form silicon nitride within the widened pinholes and to form a silicon nitride comprising layer, comprising silicon nitride of both the first and second layers.
With this method, the silicon nitride layer of the ONO dielectric composite is not reduced in thickness. As stated above, the thinner the dielectric layer, the greater the capacitance.
Therefore, it is an object of the present invention to provide a method for fabricating an ONO composite having a thinned silicon nitride layer with superior mechanical properties, such as fewer defects.
It is another object of the present invention to provide a method for fabricating an ONO composite having a thinned silicon nitride layer with superior electric properties.
It is another object of the present invention to provide a method to increase the capacitance provided by an interpoly dielectric.
It is a further object of the present invention to provide a method for fabricating an interpoly dielectric exhibiting a low leakage current and high reliability.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having the desirable characteristic of a thin silicon nitride layer with a reduced density of defects. A thin silicon nitride layer having a reduced density of defects helps to provide a high capacitance interpoly dielectric structure. Decreasing the thickness of the dielectric layer will increase the capacitance and reducing the density of defects will prevent current leakage from a floating gate of a memory cell, which is insulated by the dielectric structure.
In the formation of the ONO composite, a bottom or first silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a temporary silicon dioxide layer and ammonia. This temporary silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization. A second silicon dioxide layer is grown on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric. Surprisingly, the resulting silicon nitride layer of the ONO dielectric is thinner and has fewer defects than an ONO dielectric having a silicon nitride layer of the same thickness thinned by conventional methods, thus providing a higher capacitance dielectric structure.
The dielectric structure formed by the present invention can be used in devices such as EEPROM, EPROM and FLASH cells and in other capacitor devices.
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Good Mark A.
Kelkar Amit S.
Atmel Corporation
Kilday Lisa
Schneck Thomas
Sherry Michael
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