Method for fabrication BiCMOS integrated circuit

Details Method for fabrication BiCMOS integrated circuit Method for fabrication BiCMOS integrated circuit

1997-08-20

1998-11-24

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438307, 438370, 438371, 438373, 257370, H01L 218238

Patent

active

058406034

ABSTRACT:
A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a mask. The first photoresist layer is then removed and a second photoresist layer is formed. The second photoresist layer has opening portions in a region where an emitter region should be formed and in the region where the collector leading region should be formed. Phosphorous is implanted with taking the second photoresist layer as a mask to form an n-type selective diffusion region in a region below the region where the emitter region should be formed and in the region where the collector leading region should be formed. Then, the second photoresist layer is removed. A polycrystalline silicon layer is formed over the entire surface and arsenic is implanted therein to make it n-type. Thereafter, heat treatment is performed to form an emitter region in the region where the emitter region should be formed and an n-type diffusion layer in the region where the collector leading region should be formed.

REFERENCES:
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patent: 5288652 (1994-02-01), Wang et al.
patent: 5302534 (1994-04-01), Monk et al.
patent: 5439833 (1995-08-01), Hebert et al.
patent: 5643810 (1997-07-01), Jang
patent: 5665615 (1997-09-01), Anmo
patent: 5702959 (1997-12-01), Hutter et al.

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