Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-12
2001-03-20
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06204118
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic devices, and more particularly to a method for fabricating an open can-type stacked capacitor on local topology.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other integrated circuits. One type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and are refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit of memory, high device density and feasibility of use.
In a DRAM, each memory cell typically includes an access transistor coupled to a storage capacitor. In order to fabricate high density DRAMs, the storage capacitors must take up less planar area in the memory cells. As storage capacitors are scaled down in dimensions, a sufficiently high storage capacity must be maintained. Efforts to maintain storage capacity have concentrated on building three-dimensional capacitor structures that increase the capacitor surface area. The increased surface area provides for increased storage capacity. Three-dimensional capacitor structures include trench capacitors and stacked capacitors.
For stacked capacitors, the storage node generally extends significantly above the surface of an underlying substrate in order to provide a large surface area and thus sufficient storage capacity. This leads to topological problems in the formation of subsequent layers of the DRAM. Such topological problems are reduced by the use of open can-type stacked capacitors that use annular electrodes to increase surface area of the storage node while minimizing height. However, open can-type stacked capacitors have needed a planarized surface on which to be formed, which limits the applications in which they can be used and adds cost to the fabrication process.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved open can-type stacked capacitor and method are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides an improved method for fabricating an open can-type stacked capacitor on local topology, such as bit lines of a memory array.
In one embodiment of the present invention, a method for fabricating an open can-type stacked capacitor on local topology includes forming a conductive layer outwardly of an insulator and an access line extending from the insulator. A mask is formed outwardly of the conductive layer. A first electrode is formed by removing at least part of the conductive layer exposed by the mask. The first electrode includes an annular sidewall having a first segment disposed on the insulator and a second, opposite segment disposed on the access line. A dielectric layer is formed outwardly of the first electrode. A second electrode is formed outwardly of the dielectric layer.
Technical advantages of the present invention include providing an improved method for forming an open can-type stacked capacitor. In particular, an open can-type stacked capacitor is formed on local topology of a memory array, such as on and between access lines extending from an insulator. As a result, the underlying service need not be planarized and the cost of manufacturing a capacitor is reduced.
Another technical advantage of the present invention includes an improved method of forming a DRAM using the open can-type stacked capacitor of the present invention. Still another technical advantage is the elimination of extended wet etching processes used for planarization. Accordingly, particle generation associated with wet etching is minimized.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5451537 (1995-09-01), Tseng et al.
patent: 5459094 (1995-10-01), Jun
patent: 5595928 (1997-01-01), Lu et al.
patent: 5728617 (1998-03-01), Tseng
patent: 5885866 (1999-03-01), Chen
Boku Katsushi
Miyai Yoichi
Moroi Masayuki
Bowers Charles
Brady III Wade James
Brewster William M.
Telecjy, Jr. Frederick J.
Texas Instruments Incorporated
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