Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-12
2004-11-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S593000
Reexamination Certificate
active
06812096
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 92101439, filed on Jan. 23, 2003.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a semiconductor device that comprises a self-aligned contact and a fabrication method thereof. More particularly, the present invention relates to memory device that comprises a self-aligned contact and a fabrication method thereof.
2. Description of Related Art
The resolution in fabricating the current ultra large scale integrated (ULSI) circuit has already been developed to 0.18 microns and below. In other words, the larger the ratio of depth to line width or diameter, the contact of the semiconductor device and metal will become smaller. To overcome the continuous decrease in the line width and a misalignment of the contact is one important research and development effort that is being emphasized in the semiconductor industry.
To overcome the continuous decrease in the line width and the misalignment of the contact, semiconductor device normally employs the design of a self-aligned contact.
The conventional contact is formed between two neighboring gate structures and is in contact electrically with the source/drain regions in the substrate beside both sides of the gate structures.
However, the application of a self-aligned contact in a flash memory device has not yet been proposed. In other words, a self aligned contact is formed between two neighboring control gates, wherein the contact penetrates through the dielectric layer under the two control gates and electrically contacts with the bit line in the substrate in order to electrically connect the bit line to an external circuit.
SUMMARY OF INVENTION
Accordingly, the present invention provides a semiconductor device with a self-aligned contact and a fabrication method thereof, wherein the design of a self-aligned contact is applied to a flash memory device to electrically connect the bit line in the substrate to an external circuit.
The present invention further provides a semiconductor device with a self-aligned contact and a fabrication method thereof, wherein another application of a self-aligned contact is provided.
The present invention provides a semiconductor device with a self-aligned contact and a fabrication method thereof, wherein a plurality of first stacked layers is formed over a substrate, wherein each first stacked layer is formed with a first gate dielectric layer and a conductive layer. A cap layer is further formed over the conductive layer of the first stacked layer to protect the conductive layer. Bit lines are formed in the substrate beside two sides of each of the first stacked layers, followed by filling a first dielectric layer in between the first stacked layers. If the first stacked layers comprise a cap layer, the cap layer needs to be removed after the filling of the first dielectric layer. Thereafter, the conductive layer of the stacked layers is then patterned to a direction perpendicular to the direction of the bit lines to form a plurality of floating gates. A second dielectric layer then fills in between the floating gates. A second stacked layer is further formed above the floating gates of a same row, wherein each of the second stacked layer is formed with a thin dielectric layer, a control gate and a cap layer. Spacers are further formed on the sidewalls of the second stacked layers, followed by forming a third dielectric layer over the substrate to cover the second stacked layers. The etching rates of the spacer and the cap layer are lower than the etching rates of the third dielectric layer and the first dielectric layer. Thereafter, the third dielectric layer and the first dielectric layer are patterned to form a self-aligned contact opening between two neighboring second stacked layers, exposing the corresponding bit line. A first conductive material then fills the self-aligned contact opening to form a self-aligned contact, wherein the self-aligned contact is formed between two neighboring second stacked layers. Further, the self- aligned contact penetrates through the third dielectric layer above the second stacked layers and the first dielectric layer to electrically contact with the bit line.
The present invention provides a fabrication method for a semiconductor device with a self-aligned contact, wherein a substrate with a conductive structure already formed thereon is provided. The conductive structure is formed over a first dielectric layer, followed by forming a plurality of gate structures above the first dielectric layer, wherein each gate structure is formed with a dielectric thin layer, a gate conductive layer and a cap layer. A spacer is further formed on the sidewall of each gate structure. Thereafter, a second dielectric layer is formed over the substrate, covering the gate structure. The second dielectric layer and the first dielectric layer are then patterned to form a self-aligned contact opening between two neighboring gate structures, wherein the self-aligned contact opening exposes the conductive structure under the first dielectric layer. The self-aligned contact opening is then filled with a conductive material to form a self-aligned contact.
The present invention provides a semiconductor device that comprises a self-aligned contact, wherein this device includes a first dielectric layer, a plurality of gate structures, a spacer, a second dielectric layer and a self-aligned contact. The first dielectric layer is disposed above a substrate, and the gate structures are disposed above the first dielectric layer, wherein each gate structure comprises a dielectric thin layer, a gate conductive layer and a cap layer. A spacer is disposed on a sidewall of each gate structure. Further, the second dielectric layer is disposed to cover the first dielectric layer and the gate structures. The self-aligned contact is positioned in the first and second dielectric layers between two neighboring gate structures. In other words, the self-aligned contact is positioned between two neighboring gate structures and is penetrated through the second dielectric layer above the gate structure and the first dielectric layer.
The self-aligned contact of the present invention is formed between two neighboring gate structures and is penetrated through the dielectric layer that is underneath and in between two neighboring gate structures to electrically contact with the conductive structure under the dielectric layer. The present invention provides a self-aligned contact with a structure that is different from that in the prior art. Further, the self-aligned contact of the present invention is applicable in flash memory devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6285045 (2001-09-01), Itabashi et al.
patent: 6335243 (2002-01-01), Choi et al.
patent: 6348375 (2002-02-01), Lee et al.
Chen Kuang-Chao
Lu Jui-Lin
Yang Ling-Wuu
Fourson George
Jiang Chyun IP Office
Kebede Brook
Macronix International Co. Ltd.
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