Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-10
2004-03-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S270000
Reexamination Certificate
active
06699761
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91113448, filed Jun. 20, 2002.
BACKGROUND OF INVENTION
Field of the Invention
The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a method for fabricating a y-direction, self-alignment mask read-only memory (ROM) device.
Background of the Invention
Referring to
FIG. 1A
, the conventional fabrication process of a mask ROM device includes providing a substrate
100
. A gate oxide layer
102
is then formed on the surface of the substrate
100
. Using a patterned photoresist layer
103
as a mask, an ion implantation process
106
is conducted to form a buried drain region
108
in the substrate
100
as the bit line.
FIGS. 1A
to
1
C are schematic, cross-sectional views, illustrating the conventional fabrication process of a mask ROM device, wherein
FIGS. 1B and 1C
are views of a plane perpendicular to the plane in FIG.
1
A.
Referring to
FIG. 1A
, the conventional fabrication process of a mask ROM device includes providing a substrate
100
. A gate oxide layer
102
is then formed on the surface of the substrate
100
. Using a patterned photo layer
104
as a mask, an ion implantation process
106
is conducted to form a buried drain region
108
in the substrate
100
as the bit line.
Referring to
FIG. 1B
, after removing the patterned photoresist layer
103
, a patterned polysilicon layer
104
is formed on the gate oxide layer
102
as the word line. A patterned photoresist layer
110
is formed on the substrate
100
, exposing a channel region
114
to be coded by implantation. Further using the photoresist layer
110
as a mask, a code implantation
112
is performed to implant dopants in the channel region
114
.
Thereafter, as shown in
FIG. 1C
, the photoresist layer
110
is removed to complete the manufacturing of a mask ROM device.
However, the mask ROM device formed by the conventional approach, the coding implantation step is performed after the formation of the polysilicon layer (word line). To reach the channel region, the implantation of the coding implantation step needs to go through the polysilicon layer. Diffusion of dopants thus easily occurs to limit the reduction of the device dimension. Moreover, the mask that is being used for the ion implantation of the conventional coding implantation process is formed directly on the gate oxide layer. When a misalignment occurs between the memory device and the coding mask, ions are not implanted to the appropriate region, and the tail bit effect is generated. Therefore, the cell window of the memory device can not be increased.
SUMMARY OF INVENTION
The present invention provides a method to fabricate a y-direction, self-alignment mask read-only memory device, wherein the device dimension can be reduced.
The present invention also provides a fabrication method for a y-direction, self-alignment mask read-only memory device, wherein the tail bit effect generated in the conventional mask ROM device formed to increase the cell window of a memory device.
The present invention provides a fabrication method for a y-direction, self-alignment mask ROM device, wherein a patterned first photoresist layer is formed on a substrate and a first ion implantation is performed to form a buried drain region in the substrate using the first photoresist layer as a mask. Subsequent to the removal of the first photoresist layer, a gate oxide layer is formed on the surface of the substrate. A silicon nitride bar that is perpendicular to a direction of the buried drain region is then formed on the gate oxide layer. A patterned second photoresist layer is then formed on the gate oxide layer and the bar-shaped silicon nitride layer. Further using the second photoresist layer as ion implantation mask, a code implantation process is conducted to form a plurality of coded memory cells. The second photoresist layer is then removed, follow by forming a polysilicon layer on the gate oxide layer and on the bar-shaped silicon nitride layer. A portion of the polysilicon layer is removed until the bar-shaped silicon nitride layer is exposed by back-etching or chemical mechanical polishing. A metal silicide layer is further formed on the surface of the polysilicon layer. The bar-shaped silicon nitride layer is subsequently removed.
The present invention provides a method for fabricating a y-direction, self-alignment mask ROM device. The method includes providing a substrate, wherein the substrate comprises a memory cell region and a peripheral circuit region. Moreover, an isolation structure is already formed in the peripheral circuit region to define an active region. A first patterned photoresist layer is then formed on the substrate, covering the entire peripheral circuit region and exposing the part of the substrate that is going to be formed as the buried drain region in the memory cell region. After this, a buried drain region is formed in the substrate of the memory cell region, using the first photoresist layer as an ion implantation mask. A gate oxide layer is then formed on the surface of the substrate subsequent to the removal of the first photoresist layer. A patterned silicon nitride layer is then formed on the gate oxide layer, wherein the silicon nitride layer in the memory cell region includes a plurality of bar-shaped silicon nitride layers formed perpendicular to the buried drain region, while the silicon nitride layer in the peripheral circuit region exposes the gate oxide layer. A second patterned photoresist layer is then formed on the silicon nitride layer and the gate oxide layer. The second photoresist layer exposes a channel region in the memory cell region that is to be code implanted while covers the entire peripheral circuit region. Using the second photoresist as an ion implantation mask, a code implantation is performed to form a plurality of coded memory cells in the memory cell region. Thereafter, the second photoresist layer is removed, followed by forming a polysilicon layer on the gate oxide layer and the silicon nitride layer. Back-etching or chemical mechanical polishing is further conducted to remove a part of the polysilicon layer until the silicon nitride layer is exposed. A metal silicide layer is formed on the surface of the polysiliocn layer. The silicon nitride layer is then removed. The polysilicon and the metal silicide structure in the memory cell region forms a word line, while the polysilicon and metal silicide structure in the peripheral circuit region serves as a gate.
According to the fabrication method of a y-direction, self-alignment mask ROM device of the present invention, the bar-shaped silicon nitride layer that is perpendicular to the buried drain region forms on the gate oxide layer. Even a misalignment occurs between the coding mask and the memory device, the bar-shaped silicon nitride layer can prevent the dopants of the code implantation to be implanted at the wrong region. The present invention can thus provide the y-direction, self-alignment effect.
According to the fabrication method for a y-direction, self-alignment mask ROM device of the present invention, the coding implantation is performed before the formation of the word line, the code implantation of the channel region can achieve without having to pass through the word line to prevent the diffusion of dopants.
With the y-direction, self-alignment effect, the fabrication method for a mask ROM device of the present invention can prevent the generation of tail bit effect as in the conventional practice to increase the cell window of a memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5691216 (1997-11-01), Yen et al.
patent: 6251731 (2001-06-01), Wu
patent: 6440798 (2002-08-01), Lai et al.
Huynh Yennhu
Jiang Chyun IP Office
Macronix International Co. Ltd.
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