Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-03-21
2006-03-21
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S589000, C438S137000
Reexamination Certificate
active
07015103
ABSTRACT:
A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area. The method also includes forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area, sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer, and forming the first gate electrode by selectively patterning the conductive layer. The method further includes forming an insulating interlayer on an entire surface of the substrate including the first gate electrode, forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area, and forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.
REFERENCES:
patent: 4890144 (1989-12-01), Teng et al.
patent: 5160491 (1992-11-01), Mori
Chen Jack
DongbuAnam Semiconductor Inc.
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