Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-19
2001-01-09
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C257S321000
Reexamination Certificate
active
06171907
ABSTRACT:
The present invention relates generally to methods for fabricating nonvolatile semiconductor memory devices, and more particularly to a method for fabricating a tunnel window in an electrically-erasable-programmable read-only memory (EEPROM) cell with a reduced cell pitch.
BACKGROUND OF THE INVENTION
Electrically-erasable-programmable read-only memory (EEPROM) devices are well-known in the art. EEPROMs are a type of nonvolatile memory, a category that also includes erasable-programmable read-only memories (EPROMs) and flash memories.
EEPROMs include an array consisting of EEPROM cells arranged in rows and columns. Each row of EEPROM cells in the array is connected to a respective word line WL. Each column of EEPROM cells in the array is connected to one, or a pair of, bit lines BL.
EEPROMs support three basic operations: read, program and erase. The read operation reads the data stored in selected cells in the EEPROM. The program operation writes data to selected EEPROM cells. The erase operation erases data globally or from selected sectors of the EEPROM.
FIG. 1
is a circuit diagram for a typical EEPROM cell
100
. EEPROM cell
100
comprises two n-channel metal-oxide semiconductor (NMOS) transistors: memory transistor
101
and select transistor
102
. Memory transistor
101
stores the binary state of EEPROM cell
100
, which can be either a “0” or a “1”. Memory transistor
101
is a specially constructed transistor that includes two gates: a control gate
115
and a floating gate
116
. Control gate
115
is connected to a V
PP
signal which is set to various different voltages during read, program and erase operations. Floating gate
116
, which is electrically insulated from the rest of EEPROM cell
100
, stores a charge representing the binary state of the EEPROM cell.
Also referring to
FIG. 1
, memory transistor
101
additionally includes a tunnel window
130
. Tunnel window
130
is used to transfer charge between the drain and floating gate
116
of memory transistor
101
during a program or erase operation. The tunnel window encloses a very thin tunnel oxide layer sandwiched between floating gate
116
and the drain of memory transistor
101
through which electrons may tunnel.
Continuing to refer to
FIG. 1
, memory transistor
101
of EEPROM cell
100
further includes a source and a drain. The source of memory transistor
101
is connected to a V
PS
signal which assumes one of several different states or voltages during read, program and erase operations. The drain of memory transistor
101
is connected to the source of select transistor
102
.
Still referring to
FIG. 1
, select transistor
102
of EEPROM cell
100
couples memory transistor
101
to a bit line BL corresponding to the EEPROM cell. Select transistor
102
is a conventional transistor including a gate, a source and a drain. The gate of select transistor
102
is connected to a word line WL corresponding to the EEPROM cell. The drain of the select transistor is connected to the bit line BL. The source of the select transistor is connected to the drain of memory transistor
101
.
FIGS. 2 and 3
illustrate a conventional physical structure for an EEPROM cell
200
.
FIG. 2
is a plan view of the physical structure, while
FIG. 3
is a cross-sectional view along the lines
3
—
3
shown in FIG.
2
.
Referring to
FIGS. 2 and 3
, EEPROM cell
200
includes a memory transistor
201
and a select transistor
202
. Memory transistor
201
includes a tunnel window
230
over a buried N+ diffusion region of the memory transistor. Tunnel window
230
has a width of W
T
. As mentioned earlier, tunnel window
230
encloses a tunnel oxide layer
240
through which electrons tunnel during an EEPROM cell program or erase operation. Continuing to refer to
FIGS. 2 and 3
, EEPROM cell
200
also includes an active region
220
of width W
A
that intersects tunnel window
230
. Active region
220
includes the source, drain, and channel regions of memory transistor
201
and select transistor
202
. EEPROM cell
200
further includes a field oxide layer
225
adjacent to and surrounding active region
220
.
Still referring to
FIGS. 2 and 3
, EEPROM cell
200
additionally includes a buried N+ diffusion (BN+) layer
250
in p-type substrate
210
. BN+ diffusion layer
250
is located underneath and extends beyond the perimeter of tunnel window
230
.
Further referring to
FIGS. 2 and 3
, EEPROM cell
200
also includes a first-level polysilicon (poly1) layer
260
, an oxide-nitride-oxide (ONO) layer
265
and a second-level polysilicon (poly2) layer
270
over tunnel window
230
. Poly1 layer
260
and poly2 layer
270
form the floating gate and control gate, respectively, of memory transistor
201
.
Referring to
FIG. 2
, EEPROM cell
200
also includes a polysilicon layer
280
crossing over active region
220
. Polysilicon layer
280
forms the gate of select transistor
202
. EEPROM cell
200
further includes a contact
290
. Contact
290
connects the drain of select transistor
202
to the respective bit line BL (not shown) for EEPROM cell
200
.
For EEPROM cell
200
to function properly, tunnel window
230
must be fully enclosed by BN+ diffusion layer
250
. However, processes for fabricating EEPROM cell
200
may misalign tunnel window
230
with respect to BN+ diffusion layer
250
such that the tunnel window contacts substrate
210
. If tunnel window
230
contacts substrate
210
, a leakage current will occur at the junction formed between BN+ diffusion layer
250
and p-type substrate
210
whenever a program operation is performed. This leakage current reduces the breakdown voltage of the junction, thereby limiting the maximum voltage that can be formed at the drain of memory transistor
201
. As a result, the tunnel window misalignment increases the time required to program EEPROM cell
200
or worse, prevents the cell from being programmed.
Continuing to refer to
FIGS. 2 and 3
, conventional EEPROM cell
200
ensures that BN+ diffusion layer
250
fully encloses tunnel window
230
despite any misalignment by providing active region
220
with a width W
A
that extends beyond the tunnel window by an overlap D
A
. The width W
A
of active region
220
is thus W
T
+2D
A
, where W
T
is the width of tunnel window
230
and D
A
is the active region overlap.
Widening active region
220
ensures that BN+ diffusion layer
250
fully encloses tunnel window
230
because the width of BN+ diffusion layer
250
generally coincides with the width W
A
of active region
220
, as will now be explained. BN+ diffusion layer
250
is formed by performing an N+ ion implantation of substrate
210
that is exposed in active region
220
but covered elsewhere with a field oxide layer
225
. The ions penetrate the exposed substrate
210
in active region
220
but are stopped by the relatively thick field oxide layer
225
. As a result, BN+ diffusion layer
250
coincides with active region
220
and extends beyond tunnel window
230
by the overlap D
A
. Therefore, the active region overlap D
A
ensures that the tunnel window is fully enclosed by the BN+ diffusion layer despite any tunnel window misalignment that may occur.
For example, a typical fabrication process for EEPROM cell
200
may have an alignment tolerance for tunnel window
230
of 0.15 micrometers (&mgr;m), i.e., tunnel window
230
may be misaligned with respect to BN+ diffusion layer
250
by as much as 0.15 &mgr;m. In this case, an active region overlap D
A
of about 0.2 &mgr;m ensures that tunnel window
230
will be fully enclosed by BN+ diffusion layer
250
.
However, providing active region
220
with active region overlap D
A
increases the active region width W
A
, which has two important negative consequences for conventional EEPROM cell
200
. First, the increased active region width increases the pitch of EEPROM cell
200
by a corresponding amount. As a result, the area of the EEPROM cell is increased. Second, the increased active region width reduc
Berezny Neal
Fahmy Wael
NexFlash Technologies, Inc.
Pennie & Edmonds LLP
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