Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-04-08
1999-07-20
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438649, 438655, 438657, 438663, H01L 21283, H01L 21324
Patent
active
059267283
ABSTRACT:
A method for fabricating polycide contacts to semiconductor substrates, and more specifically for self-aligned contacts on substrates having field effect transistors (FETs) is achieved. After forming conventional FETs from a patterned first polysilicon layer provided with contact areas, an insulating layer is deposited. Self-aligned contact openings are etched in the insulating layer to the contact areas on the substrate, and a patterned polycide (second polysilicon/silicide) layer is used to form the electrical contacts and interconnections. However, in prior art when a photoresist mask and plasma etching are used to pattern a polycide layer, misalignment of the mask can result in notching in the sidewalls of the patterned second polysilicon layer resulting in contact damage and high leakage currents. The method of the present invention utilizes a critical pre-etch rapid thermal anneal (RTA) that essentially eliminates the notching during etching of these marginally misaligned contacts. This allows tighter design ground rules to be used without high leakage currents, thereby providing higher density integrated circuits with improved product yield.
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Lee Hsiang-Fan
Liaw Jhon-Jhy
Lin Yi-Miaw
Szuma Liang
Ackerman Stephen B.
Quach T. N.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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