Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-17
2000-01-18
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438238, 438237, 438979, H01L 218246
Patent
active
060157380
ABSTRACT:
A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind.
REFERENCES:
patent: 3363240 (1968-01-01), Cola et al.
patent: 4238694 (1980-12-01), Kimerling et al.
patent: 5280445 (1994-01-01), Shieh et al.
patent: 5281871 (1994-01-01), Mori et al.
patent: 5390145 (1995-02-01), Nakasha et al.
patent: 5438539 (1995-08-01), Mori
patent: 5535156 (1996-07-01), Levy et al.
patent: 5686341 (1997-11-01), Roesner
"Optical and Electrical Oscillations in Double-Heterojunction Negative Differential Resistance Devices", Kovacic et al., IEEE Trans on Electron Devices, vol. 40, No. 6 (Jun. 1993).
"A Novel Metal-Insulator Semiconductor Switch", El Badry, M.A. Sc. Thesis, University of Toronto (Feb. 1976).
"Switching in New MOS Devices and Applications", Chik, M.A. Sc. Thesis, University of Toronto (1977).
"Switching phenonmena in metal-insulator-n/p+ structures: theory, experiment and applications", Simmons et al., The Radio and Electronic Engineer, vol. 48, No. 5 (May 1978).
"Characteristics of Three-Terminal Metal-Tunnel Oxide-n/p+ Devices", Chik et al., Solid-State Electronics, vol. 22, pp. 589-594 (1979).
"Current-Mode Techniquest for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's", Seevinck et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4 (Apr.1991).
"High Speed Sending Techniques for Ultrahigh-Speed SRAM's", Nambu et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 4 (Apr. 1992).
Levy Harold J.
McGill Thomas C.
California Institute of Technology
Tsai Jey
LandOfFree
Method for fabricating transistorless, multistable current-mode does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating transistorless, multistable current-mode , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating transistorless, multistable current-mode will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-562871