Method for fabricating the control and floating gate...

Details Method for fabricating the control and floating gate... Method for fabricating the control and floating gate...

2001-08-31

2003-05-06

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S257000

Reexamination Certificate

active

06558997

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory implementable as a split-gate EEPROM, in which the control and floating gates of each storage element are formed side by side on a substrate, and also relates to a method for fabricating a memory of that type.
An electrically erasable and programmable read-only memory (EEPROM) with floating gates is known as a typical electrically erasable and programmable nonvolatile semiconductor memory.
Recently, a semiconductor memory should have its size further reduced to realize an even more densely integrated LSI and also has to have its performance further enhanced. A split-gate EEPROM was proposed as a structure that would contribute to such downsizing and performance enhancement greater than any other candidate. This is because a split-gate EEPROM includes a floating gate electrode that is horizontally adjacent to a control gate electrode with a capacitive insulating film interposed therebetween and because the split-gate EEPROM can operate even at a lower supply voltage.
Normally, in writing data on an EEPROM, a high voltage is produced between the drain region and control gate electrode to create hot electrons in part of the channel region near the drain region. Then, those hot electrons are accelerated and injected into the floating gate electrode. To erase data from an EEPROM on the other hand, the charges existing in the floating gate electrode are ejected into the source, drain or channel region by way of the tunnel insulating film.
Hereinafter, a known split-gate semiconductor memory will be described with reference to FIG.
7
.
As shown in
FIG. 7
, the semiconductor memory has memory and logic circuit regions
100
and
200
obtained by partitioning a semiconductor substrate
101
of silicon by an isolation film
102
.
On the memory circuit region
100
of the substrate
101
, a control gate electrode
104
has been formed with a gate insulating film
103
interposed therebetween. As shown in
FIG. 7
, the surface of the substrate
101
has a step
110
a
in the memory circuit region
100
. And on the side face of the control gate electrode
104
closer to the step
110
a
, a floating gate electrode
105
has been formed to cover the step
110
a
with an insulating film
106
interposed therebetween.
Source/drain regions
107
and
108
have been defined in parts of the substrate
101
beside the control and floating gate electrodes
104
and
105
, respectively. Parts of the control and floating gate electrodes
104
and
105
and source/drain regions
107
and
108
, which would be exposed otherwise, are covered with a metal silicide film
110
.
On the logic circuit region
200
of the substrate
101
, a gate electrode
112
has been formed with a gate insulating film
111
interposed therebetween. A sidewall insulating film
113
has been formed on the side faces of the gate electrode
112
. Source/drain regions
114
have been defined in parts of the substrate
101
beside the gate electrode
112
. And parts of the gate electrode
112
and source/drain regions
114
, which would be exposed otherwise, are also covered with the metal silicide film
110
.
In the known structure with the memory and logic circuit regions
100
and
200
on one substrate
101
, the control and floating gate electrodes
104
and
105
, source/drain regions
107
,
108
and
114
and gate electrode
112
have their upper surface covered with the metal silicide layer
110
entirely. Accordingly, the devices formed in the memory and logic circuit regions
100
and
200
can operate faster.
In the known memory, however, the control and floating gate electrodes
104
and
105
are adjacent to each other with the extremely thin insulating film
106
interposed therebetween. Thus, when the respective upper surfaces of the control and floating gate electrodes
104
and
105
are silicided, these electrodes
104
and
105
might be short-circuited with each other.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to further reduce the size of, and further enhance the performance of, a semiconductor memory of a split-gate type including memory and logic circuits on the same substrate.
To achieve this object, according to the present invention, the control and floating gate electrodes for the memory circuit do not have their upper surface silicided.
Specifically, a first inventive semiconductor memory includes: a control gate electrode formed over a first active region of a semiconductor substrate with a control gate insulating film interposed therebetween; and a floating gate electrode formed adjacent to a side face of the control gate electrode and over the first active region. A capacitive insulating film is interposed between the side face of the control gate electrode and the floating gate electrode, while a tunnel insulating film is interposed between the first active region and the floating gate electrode. The memory further includes: first source/drain regions defined in parts of the first active region beside the control and floating gate electrodes, respectively; and a gate electrode formed over a second active region of the substrate with a gate insulating film interposed therebetween. The second active region is electrically isolated from the first active region. The memory further includes second source/drain regions defined in respective parts of the second active region beside the gate electrode. In this memory, only the second source/drain religions and the gate electrode have their upper surface covered with a metal silicide film.
In the first inventive memory, only the second source/drain regions and gate electrode of each logical element in the second active region have their upper surface covered with a metal silicide film. That is to say, the control and floating gate electrodes of each storage element in the first active region do not have their upper surface silicided. Accordingly, the control and floating gate electrodes will not be short-circuited with each other. In addition, the upper surface of the first active region, or the memory circuit region, is not silicided. Thus, in forming contacts to electrically connect the first source/drain regions to external members, a decreased mask overlay margin is allowed, so the first active region can be downsized drastically. As a result, a semiconductor memory, including storage and logic elements for memory and logic circuits on the same semiconductor substrate, can have its size reduced considerably and its performance enhanced greatly.
A second inventive semiconductor memory includes: a control gate electrode formed over a first active region of a semiconductor substrate with a control gate insulating film interposed therebetween; and a floating gate electrode formed adjacent to a side face of the control gate electrode and over the first active region. A capacitive insulating film is interposed between the side face of the control gate electrode and the floating gate electrode, while a tunnel insulating film is interposed between the first active region and the floating gate electrode. The memory further includes: first source/drain regions defined in parts of the first active region beside the control and floating gate electrodes, respectively; and a gate electrode formed over a second active region of the substrate with a gate insulating film interposed therebetween. The second active region is electrically isolated from the first active region. The memory further includes second source/drain regions defined in respective parts of the second active region beside the gate electrode. In this memory, only the first and second source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.
The second inventive memory also achieves the effects of the first inventive memory. In addition, the control and floating gate electrodes of each storage element in the first active region do not have their upper surface silicided. Accordingly, the control and floating gate electrodes will not be sh

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