Method for fabricating stress enhanced MOS circuits

Details Method for fabricating stress enhanced MOS circuits Method for fabricating stress enhanced MOS circuits

2006-08-11

2008-10-21

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE27108

Reexamination Certificate

active

07439120

ABSTRACT:
A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.

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