Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-26
2001-09-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S003000
Reexamination Certificate
active
06284595
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a stacked capacitor and a method for fabricating a stacked capacitor in a semiconductor device. More specifically, the present invention relates to an improvement of characteristics of a stacked capacitor such as an anti-oxidation property and an electric resistance for the electrode thereof.
(b) Description of a Related Art
A semiconductor integrated circuit, such as a DRAM, often includes a stacked capacitor in a functional element constituting the semiconductor integrated circuit. It is desired along with the development of higher integration and finer patterning of the semiconductor device that the dimensions of the capacitor be reduced.
The technique for reduction of the dimensions of the capacitor is described in “1997 Symposium on VLSI Technology Digest of Technical Papers”, pp 17 and 18, for example. In the publication, a stacked capacitor is proposed which includes a Ru film for each electrode of the stacked capacitor and a high permittivity film, such as BST film, as the capacitor insulator film.
FIGS. 1A
to
1
G consecutively show fabrication steps of a conventional stacked capacitor in a semiconductor integrated circuit. In fabrication of the stacked capacitor, a plurality via-holes each receiving therein a polysilicon plug
16
are formed in a first interlevel dielectric film
14
, the polysilicon plug
16
being in contact with a diffused region formed in a semiconductor substrate
12
. A SiN film
18
is then formed on the interlevel dielectric film
14
, followed by deposition of a second interlevel dielectric film
20
, whereby the structure shown in
FIG. 1A
is obtained. The SiN film
18
is used for improvement of adhesion between the first interlevel dielectric film
14
and the second interlevel dielectric film
20
.
Subsequently, as shown in
FIG. 1B
, a photoresist film
24
is formed on the second interlevel dielectric film
20
, followed by patterning thereof to form an etching mask
24
having openings
22
therein. The second interlevel dielectric film
20
and the SiN film
18
are then subjected to patterning using the etching mask
24
to form openings
26
each exposing the contact plug
16
. Thereafter, a Ru film
28
is deposited by sputtering onto the entire area of the wafer including the inner walls of the openings
26
and on the top surface of the polysilicon plug
16
at the bottom of the opening
26
.
The Ru film
28
is then subjected to a CMP process, thereby leaving a portion of the Ru film
28
as a bottom electrode on the inner wall and the bottom of the openings
26
, as shown in FIG.
1
E. An insulator film (BST film)
30
made of (Ba,Sr)TiO
3
is then deposited on the entire area by a CVD process in an oxygen ambient. Finally, a Ru film
32
is deposited by sputtering to form a top electrode
32
, to obtain the structure shown in FIG.
1
G.
There are following problems in the conventional fabrication process for the stacked capacitor as described above. First, a high contact resistance appears between the polysilicon plug
16
and the bottom Ru electrode
28
. This is caused mainly by oxidation of the polysilicon plug
16
due to oxygen penetrating through the bottom Ru electrode
28
during CVD of the BST film
30
. The Ru film
28
has poor characteristics in stopping the penetrating oxygen due to the poor crystalline orientation alignment thereof, which in turn is caused by deposition of the Ru film
28
onto the etched surface of the openings
26
. In general, a metallic film formed on the etched surface has such a poor property. The high contact resistance reduces the read/write speed of a memory cell having the stacked capacitor.
Second, the bottom Ru electrode
28
is liable to peel-off from the inner wall of the openings
26
during the CMP process of the thin Ru film
28
. Although the Ru film
28
has excellent adherence to polysilicon, the adherence of the Ru film
28
to the first interlevel dielectric film
20
made of SiO
2
is poor. The peel-off of the bottom Ru electrode
28
may reduce the capacitance of the resultant stacked capacitor.
Third, the impurities existing at the interface between the BST film
30
and the bottom Ru electrode
28
degrade the characteristics of the resultant capacitor. The impurities include fine particles of particle slurry or Ru film left at the interface within the openings after the CMP process for the Ru film
28
. It is difficult in fact to entirely remove the remaining impurities after the CMP process. Similar situation will result if another precious metal or refractory metal is used instead of Ru.
In short, the conventional method does not provide a stacked capacitor having desired characteristics especailly for the electrodes.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a stacked capacitor having desired characteristics such as a low resistance and a higher capacitance between electrode and a method for fabricating such a stacked capacitor.
The present invention provides a stacked capacitor including a semiconductor substrate having a diffused region, a contact plug having a top surface and a bottom surface which is in contact with the diffused region, a bottom electrode in contact with the top surface of the contact plug, a capacitor insulator film formed on the bottom electrode, and a top electrode formed on the capacitor insulator film, the bottom electrode being substantially of a hollow cylindrical shape having an open top and a closed base, a vertical cross-section of the bottom electrode being substantially of a trapezoid in an outside profile thereof wherein the top of the bottom electrode has an outside dimension smaller than an outside dimension of the base of the bottom electrode.
The present invention also provides a method for fabricating a stacked capacitor including the steps of forming a first dielectric film having therein a contact plug in contact with a diffused region of a semiconductor substrate, depositing a bottom electrode layer on the first dielectric film and the contact plug, selectively etching the bottom electrode layer to form an island bottom electrode in contact with the contact plug, depositing a second dielectric film on the first dielectric film to embed the island bottom electrode, selectively etching the island bottom electrode to form a hollow cylindrical electrode having a closed bottom, depositing a capacitor insulator film on the second dielectric film and inside the hollow cylindrical electrode, and depositing a top electrode on the capacitor insulator film.
In accordance with the stacked capacitor of the present invention, the specific trapezoid shape of the bottom electrode in the vertical cross section thereof is not formed by deposition of a metallic material in an opening formed by an etching process. That is, the bottom electrode deposited on the even, smooth and non-etched surface has excellent crystalline orientation alignment.
Thus, the bottom electrode of the stacked capacitor of the present invention has excellent anti-oxidation property. This prevents the contact plug from being oxidized and increasing the contact resistance between the bottom electrode and the contact plug.
In addition, the bottom electrode is less liable to peeling-off from the dielectric film surrounding the bottom electrode because of the process wherein the bottom electrode having a hollow therein is not subjected to a CMP process. This provides the stacked capacitor with a stably high capacitance. The specific structure of the stacked capacitor of the present invention is generally formed by deposition of a metallic layer, followed by patterning thereof to form a hollow, as defined in the method of the present invention.
REFERENCES:
patent: 5474951 (1995-12-01), Han et al.
patent: 5550077 (1996-08-01), Tseng et al.
McGinn & Gibb PLLC
NEC Corporation
Tsai Jey
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