Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-20
2004-10-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S525000, C257S240000, C257S285000
Reexamination Certificate
active
06800529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor transistor device. More particularly, the present invention relates to a method for fabricating a semiconductor transistor device, which allows the saturation current of a PMOS transistor to be increased, thereby increasing the reliability of the PMOS transistor.
2. Description of the Prior Art
Generally, as the integration density of a semiconductor device increases, higher doping concentration levels in a well are required in order to improve the short channel effect caused by a reduction in the gate length of a transistor. However, an increase in the well doping concentration causes the effect of carrier scattering in a channel, so that saturation current is decreased due to a reduction in carrier mobility.
The carrier scattering effect is a phenomenon that a free carrier collides with ions with movement and loses its intrinsic energy in each collision with the ions, so that it fails to reach a target due to a reduction in velocity energy. This carrier scattering effect increases as the doping concentration in a channel region increases. Thus, the probability of the collision of the free carrier with the ions increases, so that the carrier mobility becomes smaller.
FIGS. 1
a
to
1
c
are cross-sectional views, which illustrate a method for fabricating a PMOS transistor according to the prior art.
As shown in
FIG. 1
, a device isolation film
11
is formed on a semiconductor substrate
10
, into which phosphorus ions (P
+
) impurity ions are then implanted at the ion implantation energy of 1.0E13/500 KeV and title angels of &agr;=0 degree and &bgr;=0 degree so as to form an n-type well
12
. A pad oxide film
13
is then deposited on the upper surface of the substrate
10
by an oxidation process. A punch-though stopper region
14
is then formed in the substrate
10
by an ion implantation process, after which a region for controlling channel threshold voltage
15
is formed in the substrate
10
by an ion implantation process. In forming the region for controlling channel threshold
15
, there are used As impurities, the ion implantation energy of 7.0E12/100 KeV, and the tilt angle of 7 degree.
As shown in
FIG. 1
b
, the pad oxide
13
is removed, and a gate insulating film
16
and a gate electrode
17
are successively formed on the upper surface of the resulting structure. Next, using the gate electrode
17
as a mask, impurity ions are implanted into the substrate
10
at low concentration, so that LDD regions
18
are formed in the substrate
10
at portions below both sides of the gate electrode
17
.
As shown in
FIG. 1
c
, an insulating film is then deposited on the entire structure including the gate electrode
17
, and etched back, so that insulating spacer films
19
are formed on both sides of the gate electrode
17
. Thereafter, using the insulating spacer films
19
as a mask, impurity ions are implanted into the substrate
10
, so that source/drain regions
20
are formed in the substrate
10
.
However, the prior method for fabricating the semiconductor transistor device as described above has the following problems.
When implanting impurity ions into the substrate in order to form the channel threshold voltage-controlling region, if the As impurity ions are implanted at the ion implantation energy of 7.0E12/100 KeV and the tilt angle of 7 degree, carrier mobility will be reduced due to an increase in the carrier scattering effect. As a result, saturation current is reduced, so that device characteristics are deteriorated, thereby reducing device reliability and yield.
If a SSR (super steep retrograde well) process is used in order to solve such problems, ion sources for ion implantation, which are basically different from the above method, are generally used. In the SSR process, indium is generally used instead of boron (B), and antimony (Sb) is used instead of phosphorus (P) or arsenic (As). Since these atoms has very high mass, they hardly diffuse during subsequent processes. Thus, these atoms have an advantage in that they allow a steep well profile to be realized.
However, for this purpose, an ion source needs to be connected to ion implantation equipment. Also, since these atoms cause the contamination of a chamber, the contaminated chamber must be subjected to a cleaning process after each ion implantation.
As a result, the SSR process has many problems in terms of mass production, maintenance and repair.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for fabricating a semiconductor transistor device, in which energy and tilt angle for ion implantation at ion implantation for controlling channel threshold voltage are changed, so that the doping concentration in a channel region is reduced, so as to decrease the carrier scattering effect of the device, thereby reducing the saturation current of the device.
To achieve the above object, the present invention provides a method for fabricating a semiconductor transistor device, which comprises the steps of: forming a first conductive type well in a semiconductor substrate having a device isolation film formed thereon; implanting first conductive type impurity ions into the first conductive type well so as to form a punch-through stopper region; implanting the first conductive type impurity ions into the upper portion of the resulting substrate structure at fixed tilt angle and ion energy, so as to form a channel region; forming a gate electrode including a gate insulating film on the semiconductor substrate; forming LDD regions in the semiconductor substrate at both sides of the gate electrode; forming insulating spacer films on both sides of the gate electrode; and forming source and drain regions in the semiconductor substrate at the sides of the insulating spacer films.
REFERENCES:
patent: 5296401 (1994-03-01), Mitsui et al.
patent: 5550069 (1996-08-01), Roth
patent: 5675172 (1997-10-01), Miyamoto et al.
patent: 6300201 (2001-10-01), Shao et al.
patent: 6426258 (2002-07-01), Harada et al.
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
Lee Calvin
Seyfarth Shaw LLP
Smith Matthew
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