Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1999-12-16
2001-12-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S106000, C438S126000
Reexamination Certificate
active
06331453
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging. More specifically this invention relates to a method for fabricating semiconductor packages using a mold tooling fixture with flash control cavities.
BACKGROUND OF THE INVENTION
One type of semiconductor package is referred to as a BGA package. BGA packages were developed to provide a higher lead count, and a smaller foot print, than conventional plastic or ceramic semiconductor packages. A BGA package includes an area array of solder balls that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component.
One type of prior art BGA package
10
is illustrated in FIG.
1
A. The BGA package
10
includes a substrate
12
, an array of solder balls
14
on the substrate
12
, and a semiconductor die
16
on the substrate
12
in electrical communication with the solder balls
14
. The BGA package
10
also includes a die encapsulant
18
that encapsulates the die
16
, and a wire bond encapsulant
20
that encapsulates wire bonds
22
between the die
16
and a pattern of conductors
36
on the substrate
12
. In addition, the BGA package
10
includes a solder mask
24
having openings
26
on selected areas of the conductors
36
wherein the solder balls
14
are located.
Typically the substrate
12
comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin. In addition, the substrate
12
is initially a segment of a substrate panel
12
P (
FIG. 2A
) which is similar to a lead frame used in the fabrication of conventional plastic semiconductor packages. The substrate panel
12
P includes multiple substrates
12
, and is used to fabricate multiple BGA packages
10
. Following the fabrication process for the BGA packages
10
, the substrate panel
12
P is singulated into individual BGA packages
10
.
The die encapsulant
18
and the wire bond encapsulant
20
can comprise a plastic material such as a Novoloc based epoxy formed using transfer molding process. The BGA package
10
is sometimes referred to as being “asymmetrical” because the die encapsulant
18
has a larger size and volume than the wire bond encapsulant
20
.
One problem with the asymmetrical BGA package
10
, which is illustrated in
FIGS. 1B and 1C
, occurs during molding of the wire bond encapsulants
20
. During fabrication of the BGA packages
10
on the substrate panel
12
P, the die encapsulants
18
are initially molded to the substrate panel
12
P using a first mold fixture
28
(FIG.
1
B). The first mold fixture
28
includes mold cavities
30
(
FIG. 1B
) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities
30
are configured to mold the die encapsulants
18
onto the substrate panel
12
P.
After molding the die encapsulants
18
, the wire bond encapsulants
20
are molded to the panel
12
P using a second mold fixture
32
(FIG.
1
C). The second mold fixture
32
also includes mold cavities
34
(
FIG. 1C
) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities
34
are configured to mold the wire bond encapsulants
18
on the substrate panel
12
P.
Because of the construction of the first mold fixture
28
, a relatively high clamping pressure P
1
(
FIG. 1B
) can be exerted on either side of the substrate panel
12
P for sealing the mold cavities
30
during molding of the die encapsulants
18
. However, because of the construction of the second mold fixture
32
, only a relatively low clamping pressure P
2
(
FIG. 1B
) can be exerted on one side of the panel
12
P for sealing the mold cavities
34
during molding of the wire bond encapsulants
20
.
The relatively low clamping pressure P
2
can allow excess plastic material, or “flash”, to escape from the mold cavities
34
(FIG.
1
C). The flash can deposit on the conductors
36
(FIG.
1
A), and in the openings
26
(
FIG. 1A
) in the solder mask
24
(FIG.
1
A). Depending on its location, the flash can adversely affect the solder balls
14
, and the bonded connections between the solder balls
14
and the conductors
36
.
In view of the foregoing, improved methods for controlling mold flash during fabrication of semiconductor packages are needed in the art. The present invention is directed to a method for fabricating a semiconductor package in which mold flash is contained on a selected area of the package.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for fabricating semiconductor packages, a semiconductor package fabricated using the method, and an electronic assembly that includes the package are provided.
In the illustrative embodiment, the method is used to fabricate an asymmetrical BGA semiconductor package. The package includes a substrate and a semiconductor die mounted to the substrate. Initially, the substrate is provided with a first surface having a pattern of conductors, and an array ball bonding pads. The substrate also includes an opposing second surface with a die mounting area, and a wire bonding opening between the opposing surfaces. The die is attached circuit side down to the die mounting area, and wire bonds are formed through the wire bonding opening, between die contacts on the die, and the ball bonding pads on the conductors.
Following attaching and wire bonding of the die, a die encapsulant is formed on the second surface of the substrate to encapsulate the die. The die encapsulant can be molded using a conventional mold tooling fixture having a mold cavity with a geometry corresponding to that of the die encapsulant.
Following molding of the die encapsulant, a wire bond encapsulant is molded on the first surface of the substrate to encapsulate the wire bonds. For molding the wire bond encapsulant, a mold tooling fixture includes a mold cavity, and opposing flash control cavities located on either side of the mold cavity. The flash control cavities function to collect excess encapsulant, or flash, during molding of the wire bond encapsulant. This restricts the flash to a flash area on the substrate, and prevents the flash from contaminating the ball bonding pads. In addition, the flash control cavities provide pressure relief for the pressurized molding compound within the mold cavity during molding of the wire bond encapsulant. In the illustrative embodiment the flash control cavities comprise parallel spaced grooves in the mold tooling fixture located on either side of longitudinal edges of the mold cavity.
Following the molding steps, solder balls can be bonded to the ball bonding pads to form terminal contacts for the package. Because of the absence of flash on the ball bonding pads, bonding of the solder balls and the resulting bonded connections are improved, and package reliability is improved.
The electronic assembly includes one or more packages surface mounted to a supporting substrate, such as a printed circuit board.
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patent: 5341564 (1994-08-01), Akhavain et al.
patent: 5420460 (1995-05-01), Massingill
patent: 5578261 (1996-11-01), Manzione et al.
patent: 5639695 (1997-06-01), Jones et al.
patent: 5796586 (1998-08-01), Lee et al.
patent: 2001/0002321 (2001-05-01), Castro
patent: 354043470-A (1979-04-01), None
patent: 355022873-A (1980-02-01), None
patent: 356002641-A (1981-01-01), None
patent: 358017646-A (1983-02-01), None
Bolken Todd O.
Cobbley Chad A.
Peters David L.
Tandy Patrick W.
Gratton Stephen A.
Lytle Craig P.
Micro)n Technology, Inc.
Smith Matthew
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