Method for fabricating semiconductor memory

Details Method for fabricating semiconductor memory Method for fabricating semiconductor memory

1999-08-26

2001-10-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S275000, C438S279000, C438S381000, C438S382000, C438S384000

Reexamination Certificate

active

06297084

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer and an area of a salicide layer on the cell plug layer is formed larger, for simplifying the fabrication process and securing an adequate fabrication allowance.
2. Background of the Related Art
A related art semiconductor memory will be explained with reference to the attached drawings. FIGS.
1
A~
1
E illustrate sections showing the steps of a related art method for fabricating a semiconductor memory.
Referring to
FIG. 1A
, the related art method for fabricating a semiconductor memory starts with forming a device isolating layer
2
in a device isolating region of a semiconductor substrate
1
by an STI (Shallow Trench Isolation) and forming a gate oxide film on an entire surface. A polysilicon layer for forming a gate electrode and an insulating material layer ate formed on the gate oxide film
3
in succession, and subjected to selective patterning by photolithography, to form a polygate layer
4
a
and a cap insulating layer
4
b
. In this instance, a gate electrode layer (a wordline)
6
of a cell transistor is formed in a cell region, and a gate electrode layer
7
of a driver transistor used in input/output of data is formed in a peripheral circuit region. The polygate layer
4
a
for forming a gate electrode and the cap insulating layer
4
b
are patterned with a dummy pattern in a portion of the peripheral circuit region, for use as a restrictive layer
5
for forming a circuit. Though not shown in the drawing, there are impurity regions for use as source/drain form in surfaces of the semiconductor substrate
1
on both sides of the gate electrode. Then, as shown in
FIG. 1B
, a material layer for forming gate sidewalls is formed on an entire surface inclusive of the cell region and the peripheral circuit region, a mask layer is formed of a material, such as photoresist (not shown) on the device isolation region, and etched back to form gate sidewalls
8
at sides of the gate electrode layer
6
in the cell region. As shown in
FIG. 1C
, the photoresist layer used as the mask layer in the etch back is removed. A material layer for forming a plug, for example, a polysilicon layer is formed on an entire surface, and etched back, to form a polyplug layer
9
which is in contact with the impurity regions and stuffing spaces between the gate electrodes
6
(but insulated from the gate electrode layer by the gate sidewalls). Then, as shown in
FIG. 1D
, the cell region is masked by a material layer of photoresist and the like, a material layer for forming sidewalls is formed on an entire surface of the peripheral circuit region, and etched back, to form gate sidewalls
10
. In this instance, in order not to leave the material layer for forming gate sidewalls, an overetch is made in the etch back, to etch portions of the device isolation layer
2
and the cap insulation layer
4
b
. As shown in
FIG. 1E
, a salicide layer
10
is formed on the polyplug layer
9
and the impurity region in the device isolating region, and an ILD (Inter Layer Dielectric) layer
11
is formed on an entire surface. Then, the ILD layer
11
is etched selectively until the salicide layer
10
is exposed, to form a bitline contact hole
12
.
In the forgoing related art method for fabricating a semiconductor memory, the polysilicon layer is patterned, to form the wordline as well as the resistive layer
5
in the peripheral circuit region at the same time. Then, the polyplug layer
9
is deposited and the salicide layer is formed, for improving gluing with a bitline formed later and electrical characteristics such as a contact resistance.
However, the aforementioned related art semiconductor memory has the following problems.
The use of polysilicon as a material of the wordline puts limitation in a signal transmission speed, making implementation of a high speed memory difficult. In order to solve the problem of operation speed, the material of the wordline and the bitline is replaced with metal. However, the wordline and the bitline formed of metal requires formation of the resistive layer of polysilicon additionally, resulting in entire fabrication process complicated.
The formation of salicide layer after deposition of the polyplug layer puts limitation on an area of the contact hole, and limitation on a salicide area caused by an alignment error, even within a tolerance in formation of the bitline contact hole it deteriorates a contact performance.
The overetch occurring in contact hole formation is liable to cause short with a gate electrode layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a semiconductor memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a semiconductor memory, which can simplify a fabrication process and provides an adequate fabrication allowance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a semiconductor memory includes the steps of (1) forming metal gate electrodes on a semiconductor substrate inclusive of a cell region and a peripheral circuit region, (2) forming gate sidewalls at sides of the gate electrode layers on the cell region and forming a material layer for forming a plug on an entire surface, (3) patterning the material layer for forming a plug on the peripheral circuit region, to form a resistive layer, (4) planarizing the material layer for forming a plug on the cell region, to form a plug layer which stuffs spaces between the gate electrode layers, and (5) selectively forming contact pad layers on a top of the plug layer on the cell region and a portion of the peripheral circuit region and converting into silicide.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5545581 (1996-08-01), Armacost et al.
patent: 6048795 (2000-04-01), Numasawa et al.

Affiliated with

Also associated with

Rating

Method for fabricating semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2596897