Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-12-27
2005-12-27
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S551000, C438S745000
Reexamination Certificate
active
06979616
ABSTRACT:
Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.
REFERENCES:
patent: 5061654 (1991-10-01), Shimizu et al.
patent: 6844589 (2005-01-01), Kim
patent: 2001-100005 (2001-11-01), None
Notice of Preliminary Rejection from Korean Intellectual Property Office dated Jul. 22, 2005, for Korean Application No. 2003-93887.
Cho Heung-Jae
Jang Se-Aug
Lee Seok-Kiu
Lim Kwan-Yong
Sohn Hyun-Chul
Dang Phuc T.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hynix / Semiconductor Inc.
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