Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-30
2004-06-22
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S231000, C438S276000, C438S303000
Reexamination Certificate
active
06753230
ABSTRACT:
FILED OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device with ultra-shallow super-steep-retrograde epi-channel of which gate length is less than 100 nm.
DESCRIPTION OF RELATED ARTS
Generally, in such transistors as metal-oxide-semiconductor field effect transistor (MOSFET) or metal-insulator-semiconductor field effect transistor (MISFET), a surface area of a semiconductive substrate, allocated below a gate electrode and a gate oxide layer, functions to flow electric circuits via an electric field supplied to a source and/or a drain in a state of supplying a voltage to the gate electrode. Thus, this surface area is called as a channel.
Also, properties of the above transistors rely on a dopant concentration of a channel, and a precise doping of the channel is very important since the dopant concentration determines several properties such as a threshold voltage of the transistor (V
T
), a drain current (I
d
) and so forth.
In connection to techniques for precise doping of the channel, ion implantation techniques including a well ion implantation and a channel ion implantation (alias; a threshold-voltage-adjusting ion implantation) are commonly used. The ion implantation technique is capable of forming the channel in variously diverse structures. As examples of the possible channel structures, there are a flat channel structure that has a uniform channel doping concentration keeping in depth within it, the buried channel structure wherein the channel formation occurs in a certain depth and a retrograde channel structure, wherein the channel doping concentration increases in depth.
Among the above-mentioned channels, the retrograde channel is formed by using such heavy ions as indium (I
n
), arsenic (A
s
) and antimony (S
b
) and so forth through heavy ion implantation techniques and is generally used for a highly functioned microprocessor of which the gate length is less than 0.2 &mgr;m. Also, the retrograde channel is applied to a highly functioned device having a property of a high driving current since the retrograde channel shows an effect of increasing a the surface mobility with decreasing the doping concentration of surface.
As a gate length has been decreased, a channel depth is required to become shallower. Thus, it is limited for applying the ion implantation technique to a channel of which depth is less than 50 nm.
In order to improve this limitation, an epi-channel structure had been suggested wherein the epi-channel is formed on a channel doping layer.
FIG. 1A
is a view illustrating an epi-channel structure of a semiconductor device in accordance with the prior art.
As shown in
FIG. 1A
, a gate oxide layer
12
and a gate electrode
13
are formed on a substrate
11
, and an epi-channel including an epi-layer
14
and a channel doping layer
15
is formed on the substrate
11
allocated below the gate oxide layer
12
. On lateral sides of the epi-channel, a highly concentrated source/drain extension (hereinafter referred as SDE)
16
and a source/drain area
17
are formed as well.
However, it is impossible for the above described prior art to establish an improved on/off current targeted by the semiconductor device with the epi-channel structure since it is difficult to control the loss and the diffusion of dopants from the channel doping layer
15
.
As shown in
FIG. 1B
, another approach has been proposed for establishing a step-like &dgr;-doped epi-channel to solve the above problem of the prior art.
FIG. 1B
is a diagram showing changes of a doping profile of the &dgr;-doped epi-channel in accordance with a transient enhanced diffusion (hereinafter referred as to TED) or a thermal budget. Also, it is observed that the &dgr;-doped profile is broadening because the step-like &dgr;-doping profile of the epi-channel allocated below the gate oxide layer
12
is unable to maintain a preferable &dgr;-doping profile due to the TED or the excessive thermal budget. Herein, the broadening of the &dgr;-doping profile and the preferable &dgr;-doping profile are expressed as P
2
and P
1
in
FIG. 1B
, and the gate oxide layer
12
is abbreviated as G
ox
.
Accordingly, although a &dgr;-doped epi-channel with doped and undoped epi-layers is formed, it is still limited to establish a &dgr;-doped epi-channel of which depth is less than 30 nm as dopants are diffused due to the TED or the excessive thermal budget. The dopant profile after excessive diffusion of the &dgr;-doped dopants are shown as D in FIG.
1
B.
As one solution for this limitation, it is suggested to restrain the diffusion of the &dgr;-doped epi-channel by instantaneously performing a laser thermal annealing (hereinafter referred as to LTA) process after forming the &dgr;-doped channel doping layer
24
in FIG.
2
A. With a required concentration through an ultra low energy ion implantation technique.
FIGS. 2A and 2B
are cross-sectional views illustrating the above described method.
With reference to
FIGS. 2A and 2B
, it is described a method of prior art for fabricating a semiconductor device with an epi-channel by the ultra low energy ion implantation and the LTA techniques.
Referring to
FIG. 2A
, P-type dopants are ion implanted on a substrate
21
formed with a field oxide layer
22
in a shallow trench isolation (STI) structure so as to form a deep P-type well
23
. Subsequently, boron ions having about 1 keV of the ultra low energy are implanted thereto, forming a &dgr;-doped channel doping layer
24
.
Next, the LTA with a unit energy level ranging from about 0.36 J/cm
2
to about 0.44 J/cm
2
is directly performed without preceeding a pre-amorphization process for making a surface of the substrate
21
amorphous.
FIG. 2B
shows the result from a direct application of the LTA, in which boron ions are redistributed forming the resultant &dgr;-doping layer
24
A with the suppression of TED.
Referring to
FIG. 2B
, an epi-layer
25
is formed through a selective epitaxial growth (hereinafter referred as to SEG) on the channel doping layer
24
A so as to form a super-steep-retrograde (hereinafter referred as to SSR) epi-channel structure. The thickness of above epi-layer
25
ranges from about 50 Å to about 300 Å, formed at a temperature ranging from about 600° C. to about 800° C. Meanwhile, it is also possible to suppress the TED of the &dgr;-doped channel doping layer
24
through a rapid thermal annealing (hereinafter referred as to RTA) in addition to the LTA.
FIG. 3A
is a graph showing a doping profile of the SSR epi-channel formed by the selective epitaxial growth on the sample doped with boron ions (B
+
) in 1 keV, while
FIG. 3B
is a graph showing a doping profile of the SSR epi-channel formed by the selective epitaxial growth on the sample doped with boron ions (B
+
) in 5 keV.
Referring to
FIGS. 3A and 3B
, with respect to the doping profile of the SSR epi-channel through the ultra low energy ion implantation, as lowering the ion implantation energy, a distribution range of the &dgr;-doping becomes narrower, and this narrow distribution of the &dgr;-doping can reduce significantly a junction capacitance of a semiconductor device. Also, it is possible to decrease the leakage currents of the junction, thereby ultimately manufacturing a semiconductor device with a low consumption of electricity and high efficiency. Therefore, this ultra low energy ion implantation technique is an essential technology to produce the above functioned semiconductor.
However, the ultra low energy ion implantation technique has a difficulty in extracting ion beams at the ultra low energy, and this difficulty results in limiting usable energies and in low productivity for establishing the doping profile for the SSR epi-channel.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating semiconductor devices with epi-channel structure that overcome the limitations in useable energy and the decrease of productivity when
Joo Sung-Jae
Sohn Yong-Sun
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Picardat Kevin M.
LandOfFree
Method for fabricating semiconductor device with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3362782