Method for fabricating semiconductor device including MIS...

Details Method for fabricating semiconductor device including MIS... Method for fabricating semiconductor device including MIS...

1999-06-15

2001-12-04

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S204000, C438S234000

Reexamination Certificate

active

06326253

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device serving as a Bipolar/CMOS device (abbreviated as “Bi-CMOS device”), in which a bipolar transistor operating at a radio frequency and an MOS transistor are both integrated on a single substrate.
Examples of transistors currently used most commonly include a bipolar transistor, which is made up of emitter, base and collector, and an MOS transistor, which is made up of gate electrode, gate oxide film and source/drain layers. The bipolar transistor is particularly suitably used as an analog devise by taking advantage of its linear amplifying capability. On the other hand, the MOS transistor has a simpler construction, and is particularly suitably implementable as a logical element. In recent years, bipolar transistors are more and more often adapted to operate at a radio frequency. Accordingly, the implementation of bipolar transistors operative at an even higher frequency is awaited. As for MOS transistors, downsizing of these devices is in high demand to further increase the number of MOS transistor devices integrated on a single chip.
In addition, miniaturization of a semiconductor device, including both a bipolar transistor operating at a radio frequency and an MOS transistor, is also required these days. To cut down the size of such a semiconductor device, a single-chip implementation, or forming both of these types of devices on a single substrate, is an effective measure to be taken. Thus, a so-called “Bi-CMOS device”, which integrates bipolar and MOS transistors on a common substrate, was suggested.
Hereinafter, an exemplary structure of a conventional Bi-CMOS device will be described with reference to accompanying drawings.
FIG. 16
is a cross-sectional view illustrating a structure of a conventional Bi-CMOS device.
As shown in
FIG. 16
, the conventional Bi-CMOS device includes a bipolar-transistor-forming region Rbp and an MOS-transistor-forming region Rmos, which consists of PMOSFET-and NMOSFET-forming regions Rpmos and Rnmos, within a silicon substrate
101
and an epitaxial layer
107
formed thereon. In this specification, the substrate
101
and the epitaxial layer
107
will sometimes be collectively referred to as a “sustrate”.
N-type buried layers
181
and
182
are formed to be electrically isolated from each other under the bipolar-transistor-forming region Rbp and under the PMOSFET-forming region Rpmos of the MOS-transistor-forming region Rmos, respectively.
On the surface of the substrate, field oxide films
111
b
,
111
d
and
111
e
and cap oxide films
119
a
and
119
b
are formed by an ordinary LOCOS process. Under each of these cap oxide films
119
a
and
119
b
, buried polysilicon layer
118
(which has been formed by filling a trench with polysilicon), trench sidewall oxide film
116
and channel stopper layer
117
are provided.
The bipolar transistor includes: collector diffused layer
140
; extrinsic base diffused layer
141
a
; intrinsic base diffused layer
141
b
; emitter diffused layer
142
; base electrode
143
; emitter electrode
145
; and collector electrode
146
. The collector diffused layer
140
is formed by epitaxy on the n-type buried layer
181
. The extrinsic and intrinsic base diffused layers
141
a
and
141
b
are formed on the collector diffused layer
140
. The emitter diffused layer
142
is located on the intrinsic base diffused layer
141
b
. And the base, emitter and collector electrodes
143
,
145
and
146
are in contact with the extrinsic base diffused layer
141
a
, emitter diffused layer
142
and collector wall
121
, respectively. The bipolar transistor further includes: TEOS film
144
on the base electrode
143
; silicon dioxide film
147
formed on the sides of the base electrode
143
by oxidizing polysilicon; and silicon nitride film
148
and polysilicon sidewall
149
interposed between the base and emitter electrodes
143
and
145
.
The PMOSFET includes: p
+
-type source/drain layers
151
; p
−
-type source/drain (LDD) layers
152
; gate oxide film
131
gate electrode
156
; and polysilicon sidewall
160
. The NMOSFET includes: n
+
-type source/drain layers
153
; n
−
-type source/drain (LDD) layers
154
; gate oxide film
131
gate electrode
158
; and polysilicon sidewall
160
.
In the PMOSFET-forming region Rpmos, PMOSFET threshold control layer
123
, punchthrough stopper layer
124
, channel stopper layer
125
covering an area from a region just under the cap oxide film
119
b
to a region just under the field oxide film
111
d
, and n-well layer
126
are formed.
In the NMOSFET-forming region Rnmos, NMOSFET threshold control layer
128
, channel stopper layer
129
covering an area from a region just under the field oxide film
111
d
to a region just under the field oxide film
111
e
, and p-well layer
130
are formed.
In the conventional fabricating process of this Bi-CMOS device, the base electrode
143
is formed to make electrical contact with the extrinsic base region
141
a
in the bipolar transistor by depositing and patterning a polysilicon film with a thin oxide film left in the interface between the base electrode
143
and the substrate. The polysilicon film is deposited posited on the oxide film, because the existence of the oxide film can prevent the polysilicon film from growing abnormally (or an excessive epitaxial growth thereof), which is observed with a polysilicon film growing on a single crystal silicon layer, for example. Also, in the conventional process, the base electrode
143
of the bipolar transistor and the respective gate electrodes
156
and
158
of the p- and n-channel MOS transistors are all formed out of this polysilicon film. And the residual interfacial oxide film is broken down by annealing at an elevated temperature, thereby reducing the contact resistance between the base electrode and the extrinsic base diffused layer.
However, according to the conventional method for fabricating a Bi-CMOS device, an oxide remains here and there in the interface between the base electrode and the extrinsic base diffused layer, and the contact resistance adversely increases at those sites. Nevertheless, if the thickness of the oxide film is reduced to suppress the increase in contact resistance, then the abnormal growth of the polysilicon film cannot be restricted sufficiently. In addition, since the high-temperature annealing promotes the diffusion of the extrinsic base diffused layer, the base-collector capacitance cannot be reduced sufficiently. In particular, to make a semiconductor device operative at an even higher frequency, the parasitic capacitance thereof should be reduced. If the area of an active region is decreased to reduce the parasitic capacitance, however, the extrinsic base diffused layer might possibly contact the emitter diffused layer.
Also, it was recently found that if the thickness of the oxide film is reduced, then the grain size of crystals is very likely to increase excessively due to the epitaxial growth happening in the interface between the epitaxial layer and the polysilicon film deposited thereon. Accordingly, the resulting performance of the bipolar transistor is much more likely to be inconstant.
FIG.
14
(
a
) is a graph illustrating respective dependence of maximum current gain cutoff frequency fT
max
and emitter-base breakdown voltage BV
EBO
on the diffusion length L of the extrinsic base diffused layer, which is defined as illustrated in FIG.
14
(
b
). The data shown in FIG.
14
(
a
) was obtained on a bipolar transistor shown in FIG.
14
(
b
), where a lateral distance from an end face of the base electrode at a lower edge of the sidewall to the surface of the sidewall was about 0.19 &mgr;m. On and after the diffusion length L of the extrinsic base diffused layer as measured from the end face of the base electrode exceeds 0.19 &mgr;m, the extrinsic base diffused layer contacts the emitter diffused layer. Accordingly, as shown in FIG.
14
(
a
), the emitter-base breakdown voltage BV
EBO
decreases a

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