Method for fabricating semiconductor device having recessed...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S589000, C257SE21618

Reexamination Certificate

active

07833870

ABSTRACT:
A semiconductor device is fabricated having a stack gate structure where a first gate electrode, a second gate electrode and a gate hard mask are stacked. The stack gate structure secures a contact open margin while reducing a loss of the gate hard mask during a self-aligned contact (SAC) etching process of forming a landing plug contact. An intermediate connection layer is formed in a landing plug contact region between the first gate electrodes. Furthermore, the occurrence of a bridge between a gate and a contact can be prevented while forming the landing plug contact. A conductive material is filled into a gate region including a recess between intermediate connection layers to form the first gate electrode. The second gate electrode and the gate hard mask are formed during a gate-patterning process using a gate mask, even though misalignment occurs between the gate and the contact.

REFERENCES:
patent: 7071059 (2006-07-01), Kim
patent: 7205606 (2007-04-01), Tran
patent: 2006/0270153 (2006-11-01), Lee
patent: 10-2005-0089294 (2005-09-01), None
patent: 100620655 (2006-08-01), None
patent: 1020070017655 (2007-02-01), None
J.Y. Kim et al., The Breakthrough in Data Retention Time of DRAM Using Recess-Channel-Array Transistor (RCAT) for 88nm Feature Size and Beyond. 2003 IEEE, pp. 11-12.
J.Y. Kim et al., S-RCAT (Sphere-Shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM Feature Size and Beyond. 2005 IEEE, pp. 34-35.

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