Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-05-22
2007-05-22
Pham, Thanhha S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S630000
Reexamination Certificate
active
11034948
ABSTRACT:
The semiconductor device comprises a gate electrode26formed on a semiconductor substrate10,a source region45a having a lightly doped source region42aand a heavily doped source region44a, a drain region45bhaving a lightly doped drain region42band a heavily doped drain region44b,a first silicide layer40cformed on the source region, a second silicide layer40dformed on the drain region, a first conductor plug54connected to the first silcide layer and a second conductor plug54connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region. Thus, even with the silicide layer formed on the source/drain region, sufficiently high withstand voltages of the high withstand voltage transistor can be ensured. Furthermore, the drain region alone has the above-described structure, whereby the increase of the source-drain electric resistance can be prevented while high withstand voltages can be ensured.
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European Search Report with Annex dated Jun. 21, 2006, issued in corresponding European Patent Application No. 03020593.4.
Asada Hitoshi
Inoue Hiroaki
Fujitsu Limited
Pham Thanhha S.
Westerman, Hattori, Daniels & Adrian , LLP.
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