Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-20
2002-01-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000
Reexamination Certificate
active
06335242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a structure of a stacked capacitor type memory cell and a method for forming the same.
2. Description of Related Art
Recently, with an increased integration density of a DRAM (dynamic random access memory), a cell size has reduced, so that there is an inclination that an occupying area of a DRAM cell is reducing as 1.6 &mgr;m
2
in 64 Mbit DRAM and 0.7 &mgr;m
2
in 256 Mbit DRAM. Therefore, in order to ensure a sufficient capacitance of a capacitor, a stacked capacitor is used which can increase a capacitor surface area per an occupying area. Ordinarily, the stacked capacitor is stacked over a transfer gate transistor.
In the DRAM cell having the above mentioned stacked capacitor structure, in order for the capacitor to have the capacitance required for an operation, it is demanded to increase the area of opposing electrodes of the capacitor. To meet this demand, a method of forming convexes and cancaves on the surface of the electrodes is adopted.
Japanese Patent Application Pre-examination Publication No. JP-A03-263370 and its corresponding U.S. Pat. No. 5,290,729 (the content of
which is incorporated by reference in its entirety into this application) disclosed a technology for forming convexes and cancaves on the surface of a lower electrode. According to this technology, a silicon layer having a concavo-convex surface is formed on the whole of the surface of a silicon substrate, and a phosphorus-doped polysilicon layer is formed on the silicon layer. Then, a heat treatment is conducted to cause the phosphorus contained in the polysilicon layer to diffuse into the inside of the silicon layer so that the silicon layer acquires electric conductivity. Thereafter, the stacked layer of the polysilicon layer and the silicon layer is patterned into a shape of an electrode, so that a lower electrode having convexes and cancaves on an upper surface is formed.
In this prior art lower electrode, however, only the upper surface has the convexes and cancaves, and a side surface of the lower electrode is flat. There is a limit in increasing the electrode area by forming the convexes and cancaves on only the upper surface.
Under this circumstance, Japanese Patent Application Pre-examination Publication No. JP-A-05-304273 (now, Japanese Patent No. 2,508,948, and an English abstract of JP-A-05-304273 is available and the content of the English abstract is incorporated by reference in its entirety into this application) proposes a method for forming a polysilicon as a capacitor electrode in the DRAM cell, this method enabling to form the convexes and cancaves on not only the upper surface but also the side surface, thereby to increasing the electrode surface area.
Now, the method for forming the DRAM cell in accordance with this proposed method will be described with reference to
FIGS. 9A
to
9
D, which are diagrammatic sectional views for illustrating the process for forming the DRAM cell in accordance with the proposed method. In these figures, as regards a transistor part, there is shown only an N-diffused layer
14
acting a source region (or electrode) and formed in a transistor forming zone confined by a field oxide film
12
formed on a P-type silicon substrate
10
.
As shown in
FIG. 9A
, over the transistor, an interlayer insulator film
16
is formed, and an contact hole
18
is formed in the interlayer insulator film
16
at a position of the N-diffused layer
14
. An amorphous silicon layer
20
containing a high concentration of phosphorus is formed in the inside of the contact hole
18
and on an upper surface of the interlayer insulator film
16
, and then, the amorphous silicon layer
20
is patterned by a lithography and a dry etching.
Then, as shown in
FIG. 9B
, a disilane (Si
2
H
6
) is irradiated while heat-treating the patterned phosphorus-doped amorphous silicon layer
20
in a high vacuum condition, so that silicon crystal nuclei are generated. This is because the disilane is decomposed at dangling bonds existing at a surface of the amorphous silicon layer, so as to generate crystal nuclei. Succeedingly, the heat-treatment is continuously performed in the high vacuum condition, so that crystal nuclei grow to mushroom-shaped crystalline grains
22
having a drain diameter of 60 nm to 70 nm. In the following, this crystalline grain
22
will be called a HSG (hemi-spherical (silicon crystalline) grain). Thus, a lower electrode having convexes and concaves of HSGs on an upper surface and a side surface of the phosphorus-doped amorphous silicon is formed.
Thereafter, as shown in
FIG. 9C
, a silicon nitride (SiN) film is formed on the lower electrode to form a capacitor dielectric film
24
. Furthermore, as shown in
FIG. 9D
, a polysilicon layer containing a high concentration of phosphorus is formed, and phosphorus is doped so as to form an upper electrode
26
. Thus, a stacked capacitor
28
is fabricated.
However, the stacked capacitor having the lower electrode the convexes and concaves of HSGs on the upper surface and the side surface of the phosphorus-doped amorphous silicon, has the following problem:
Namely, the HSGs has the nature of growing while discharging the impurity (phosphorus) contained therein- As a result, the post-grow HSGs are formed of non-doped silicon. This means that a surface of the lower electrode is depleted. Therefore, as shown in
FIG. 10
, the bias voltage dependency of the capacitance of the capacitor becomes remarkable, so that when the potential of the lower electrode is high, the capacitance substantially drops. Incidentally, in
FIG. 10
, the axis of abscissas indicates the bias voltage V of the upper electrode when it is compared with the voltage of the lower electrode as a reference. Assuming that when the bias voltage is 0 (zero) the capacitance is expressed as Csmax, when the bias voltage becomes minus, namely, when the potential of the lower electrode becomes high, the width of the depletion layer increases with the result that the amount of stored charges decreases and therefore the holding characteristics is deteriorated. Therefore, as shown in
FIG. 10
, when the bias voltage V of the upper electrode is at −1.5 V, the ratio of the capacitance Cs to Csmax drops to 0.7. As such, the capacitance of the capacitor depends upon the bias voltage.
The above mentioned bias voltage dependency of the capacitance is directly attributable to the non-doped condition of the surface polysilicon film after the HSG growth. In addition to this cause, since the temperature of a heat treatment in later steps has lowered with an advanced microfabrication of the design rule, the impurity contained in a high-concentration doped layer constituting the lower electrode has become hardly to re-diffuse into the HSGs after the HSG growth.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a stacked capacitor and a method for forming the same, which have overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a stacked capacitor having less bias voltage dependency of the capacitance, and a method for forming the same.
A further object of the present invention is to provide a memory cell having the above mentioned stacked capacitor having less bias voltage dependency of the capacitance, and a method for fabricating the same.
The above and other objects of the present invention are achieved in accordance with the present invention by the conception of the present invention that the depletion of the lower electrode surface can be minimized if it is possible to compensate for the loss of impurity at the surface of the mushroom-shaped crystalline grains formed of polysilicon and formed on the upper surface and the side surface of the lower electrode formed of impurity-doped polysilicon.
The compensating method includes three approaches. A first approach is to form a high-concentration impurity-doped polysilicon film on the s
McGinn & Gibb PLLC
NEC Corporation
Tsai Jey
LandOfFree
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