Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-23
2003-03-25
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06537874
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device fabrication technique, more specifically a semiconductor device including DRAM-type memory device, and a method for fabricating the same.
A DRAM is a semiconductor device which can be formed of one transistor and one capacitor. Various structures and fabrication methods have been conventionally studied for semiconductor devices of higher density and higher integration. Especially for a structure of a capacitor of a DRAM, which much influences higher integration, it is significant how to ensure a required storage capacitance without preventing higher integration of the device.
For higher integration, it is essential to reduce a memory cell area and to reduce also an area where a capacitor is to be formed. Then, it has been proposed that a column-shaped or a cylindrical capacitor structure is used so that the capacitor can have a surface area which is increased in the direction of the height, whereby a required storage capacitance can be ensured without increasing an area occupied by a region where the capacitor is formed.
A method for fabricating a conventional semiconductor device having a cylindrical capacitor structure will be explained with reference to
FIGS. 41A-41C
,
42
A-
42
B, and
43
A-
43
B. A method for fabricating a conventional semiconductor device having a column-shaped capacitor structure has the same basic fabrication process.
First, in the same way as in the method for fabricating a usual MOS transistor, a memory cell transistor including a gate electrode
102
and source/drain diffused layers
104
,
106
, and a peripheral circuit transistor including a gate electrode
108
and a source/drain diffused layer
110
are formed on a silicon substrate
100
.
Next, a bit line
114
electrically connected respectively to the source/drain diffused layer
104
through a plug
112
and an interconnection layer
116
electrically connected to the source/drain diffused layer
110
through a plug
115
are formed on an inter-layer insulation film
118
covering the memory cell transistor and the peripheral circuit transistor. In the figure, the bit line
114
is indicated by the dotted line because the bit line
114
does not appear in the shown section.
Then, an inter-layer insulation film
120
is formed on the inter-layer insulation film
118
having the bit line
114
and the interconnection layer
116
formed thereon (FIG.
41
A).
Next, a plug
124
electrically connected to the source/drain diffused layer
106
through a plug
122
is buried in the inter-layer insulation films
120
,
118
(FIG.
41
B).
Then, on the inter-layer insulation film
120
with the plug
124
buried in, an etching stopper film
126
of, e.g., a silicon nitride film, an inter-layer insulation film
128
of, e.g., a silicon oxide film, an etching stopper film
130
of, e.g., a silicon nitride film, an inter-layer insulation film
132
of, e.g., a silicon oxide film, and a hard mask
134
of, e.g., an amorphous silicon film are sequentially formed by, e.g., CVD method.
Then, the hard mask
134
, the inter-layer insulation film
132
, the etching stopper film
130
, the inter-layer insulation film
128
and the etching stopper film
126
are patterned by the lithography and etching to form an opening
136
down to the plug
124
(FIG.
41
C).
Then, a storage electrode
138
connected to the plug
124
is formed along the inside wall and the bottom of the opening
136
(FIG.
42
A).
Next, with the etching stopper film
130
as a stopper, the inter-layer insulation film
132
is isotropically etched to expose the outside surface of the storage electrode
138
(FIG.
42
B). The etching stopper film
130
and the inter-layer insulation film
128
function as a support for preventing the storage electrode
138
from falling down or peeling off in the steps following the etching step.
Then, a dielectric film of, e.g., Ta
2
O
5
film or BST film is formed on the entire surface by, e.g., CVD method to form a capacitor dielectric film
140
of the dielectric film, covering the storage electrode
138
.
Next, a conducting film is deposited on the entire surface by, e.g., CVD method and patterned to form a plate electrode
142
of the conducting film, covering the storage electrode
138
interposing the capacitor dielectric film
140
therebetween (FIG.
43
A).
Thus, a capacitor including the storage electrode
138
, the capacitor dielectric film
140
and the plate electrode
142
and connected electrically to the source/drain diffused layer
106
of a memory cell transistor is formed.
Then, a silicon oxide film is deposited on the entire surface by, e.g., CVD method, and the surface of the silicon oxide film is planarized to form an inter-layer insulation film
144
of the silicon oxide film.
Next, a contact hole
146
is formed by the lithography and etching through the inter-layer insulation film
144
, the etching stopper film
130
, the inter-layer insulation film
128
, the etching stopper film
126
and the inter-layer insulation film
120
.
Then, a plug
148
connected to the interconnection layer
116
is formed in the contact hole
146
(FIG.
43
B).
Next, an interconnection layer (not shown) connected to the plug
148
, etc. are formed.
Thus, a DRAM comprising memory cells each having one transistor and one capacitor is fabricated.
As described above, in the conventional method for fabricating the conventional semiconductor device, the etching stopper film
130
and the inter-layer insulation film
128
are provided to thereby prevent the storage electrode
138
from falling down or peeling off in the process, and the semiconductor device including the cylindrical capacitor can be fabricated.
On the other hand, a method which prevents the storage electrode
138
from peeling off without the use of the support has been proposed. Another conventional method for fabricating a semiconductor device, which uses no support for a storage electrode
138
will be explained with reference to
FIGS. 44A-44B
,
45
A-
45
B, and
46
A-
46
B.
First, in the same way as in the semiconductor device fabrication method shown in
FIG. 41A
, a memory cell transistor, a peripheral circuit transistor, a bit line
114
, an interconnection layer
116
, inter-layer insulation films
118
,
120
, etc. are formed on a silicon substrate
100
(FIG.
44
A).
Then, an etching stopper film
126
of, e.g, a silicon nitride film is formed on the inter-layer insulation film
120
by, e.g., CVD method.
Next, the etching stopper film
126
is patterned by the lithography and etching to be removed in a region where a contact hole for connecting the plug
122
to a storage electrode
138
to be formed later is to be formed.
Next, an inter-layer insulation film
132
of, e.g., a silicon oxide film, and a hard mask
134
of, e.g., an amorphous silicon film are formed on the patterned etching stopper film
126
by, e.g., CVD method in the stated order.
Then, the hard mask
134
is patterned by the lithography and etching to remove the hard mask
134
in the region where the storage electrode
138
is to be formed (FIG.
44
B).
Next, with the hard mask
134
as a mask and with the etching stopper film
126
as a stopper, the inter-layer insulation films
132
,
120
,
118
are anisotropically etched to form an opening
136
down to the plug
122
through the inter-layer insulation film
132
, the etching stopper film
126
, the inter-layer insulation films
120
,
118
(FIG.
45
A).
Then, the storage electrode
138
connected to the plug
122
is formed along the inside wall and bottom of the opening
136
(FIG.
45
B).
Then, with the etching stopper film
126
as a stopper, the inter-layer insulation film
132
is isotropically etched to expose the outside surface of the storage electrode
138
(FIG.
46
A).
The storage electrode
138
also functions as a plug for connection to the plug
122
, and is formed, buried in the inter-layer insulation films
118
,
120
, whereby the storage electrode
138
is prevented from falling down or peeling off in the s
Fukuda Masatoshi
Nakamura Shunji
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Tsai Jey
LandOfFree
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