Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

2002-08-16

2003-07-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S149000, C438S231000, C438S257000, C438S268000, C438S752000, C257S019000, C257S616000

Reexamination Certificate

active

06599803

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The disclosure relates generally to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a highly integrated semiconductor device with a design rule of under 0.1 &mgr;m.
2. Description of Related Art
Generally, a metal oxide semiconductor field effect transistor (MOSFET) of a semiconductor device includes a source/drain region and a gate region isolated by a dielectric layer on a channel region limited to the area between the source/drain regions. The source/drain region is doped to form a deep junction, and if a voltage is supplied to the gate and it surpasses a predetermined threshold value, the channel between the source and the drain becomes conductive and the transistor is turned on, thus flowing electron carriers from the source to the drain.
However, the transistor may be damaged by the hot carrier injection of high-speed electrons that impact the silicon/substrate interface formed between the source and the gate, for example, a silicon oxidation layer or a silicon interface, which is called the hot carrier effect.
The hot carrier effect occurs when the kinetic energies of exited carriers such as holes and electrons are increased as the carriers are accelerated and trapped into the gate dielectric layer through the sharp variation of their potentials. The sharp variation of the potential occurs, apparently, around the drain during the saturated operation of transistors. A huge electric field, generated by the sharp variation of the potential, is exhibited in the side junction part of a drain that neighbors channels. Hot carriers lose their energies by impact ionization when they move through the drains. As a result, an electron hole pair (EHP) is generated and moves to a gate dielectric layer around the drain junction part, and is injected to a gate dielectric layer.
To overcome the problem of hot carrier effect and other related problems, the “lightly doped drain” (LDD) structure has been suggested. The LDD structure decreases the extent of variation of the potential around the drain during saturated operation of a transistor.
However, in a method of fabricating a transistor with the LDD structure, the silicon substrate is inevitably damaged in the process of ion-injecting a low-concentration impurity for forming an LDD region and the process of ion-injecting a high-concentration impurity for forming a highly concentrated source/drain region. Also, a short channel effect, that is, shortening of the actual channel length, occurs by an annealing process performed after the source/drain ion injection in order to diffuse the ions injected in the prior process.
As a result, due to the short channel effect, the depletion layer around the drain reaches the source region, and a current uncontrolled by voltage leaks a great deal, thus causing a punch-through phenomenon in which the function of the electric field transistor is lost. Also, the properties of the device deteriorate because the threshold voltage of the device is changed.
To solve the problem of the LDD structure described above, a technique of a single drain cell (SDC) has been proposed. With a reduced surface resistance, formation of sharp junction, low contact resistance, reduced thermal budget, and easy formation of silicide, the SDC technique shows wide applicability.
FIGS. 1A and 1B
are cross-sectional views illustrating a method for fabricating a conventional single drain cell.
As shown in
FIG. 1A
, after a gate insulation layer
12
and a gate electrode
13
are formed in order on a silicon substrate
11
, a spacer
14
contacting both sidewalls of the gate electrode
13
is formed.
Subsequently, the silicon substrate
11
exposed after forming the spacer
14
, i.e., regions for source and drain, are dry-etched or wet-etched to a predetermined depth, using the spacer
14
and the gate electrode
13
as an etching mask.
As shown in
FIG. 1B
, a source/drain
15
is formed on the etched silicon substrate
11
by depositing a doped silicon layer with a chemical vapor deposition (CVD) method.
In this SDC technique, the core technology is to etch the silicon substrate vertically and horizontally with the same ratio because it is important to etch the silicon substrate to have an isotropic property.
However, in this conventional technology, since the exposed silicon substrate is directly dry- or wet-etched directly, it is difficult to form a proper etching pattern of the silicon substrate, i.e., depth and shape, for forming the source/drain region.
SUMMARY OF THE DISCLOSURE
The disclosure provides a method for fabricating a semiconductor device appropriate for embodying an isotropic etching profile when etching a silicon substrate and forming a single drain cell.
In accordance with the disclosure, a method of fabricating a semiconductor device is provided, comprising the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by removing the silicon germanium layer; and e) growing the epitaxial silicon layer doped on the opened source/drain region.


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