Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-17
2003-03-11
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S200000, C438S230000, C438S241000, C438S632000, C438S633000, C438S692000, C438S698000
Reexamination Certificate
active
06531353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device that reduces defects of a device by improving the process to improve the production yield.
2. Background of the Related Art
Generally, in a fabricating process of a Merged DRAM on Logic (MDL) device, a source, a drain, and a silicide are formed in a logic region and then an Inter Layer Dielectric (ILD) process for fabricating a DRAM cell capacitor is performed.
Also, with high packing density of a semiconductor device, a pitch of a wordline decreases, so that the ILD process necessarily requires a flowing process at a high temperature.
However, the flowing process, which is performed at a high temperature after forming the logic device, degrades characteristic of the logic device, so that defects of the device occur.
A related art method for fabricating a semiconductor device will be described with reference of the accompanying drawings.
FIG. 1A
to
FIG. 1F
are sectional views illustrating fabricating process steps of a related art semiconductor device.
First, as shown in
FIG. 1A
, a field oxide film
12
is formed in a predetermined region of a semiconductor substrate
11
by a shallow trench isolation (STI) process to define an active region.
Then, a gate oxide film and a polysilicon film are deposited on the semiconductor substrate
11
. The polysilicon film and the gate oxide film are selectively removed by photolithography and etching processes to remain on a predetermined region of the semiconductor substrate
11
corresponding to a logic region, so that a plurality of logic gates
13
a
are formed.
Subsequently, a gate oxide film, a polysilicon film, a tungsten film, a silicon nitride film, and an oxide film are sequentially deposited on an entire surface of the semiconductor substrate
11
. The oxide film, the silicon nitride film, the tungsten film, the polysilicon film, the gate oxide film are selectively removed by photolithography and etching processes to remain on a predetermined region of the semiconductor substrate
11
corresponding to a DRAM peripheral region and a DRAM cell region, so that a plurality of DRAM gates
13
b
are formed.
Lightly doped impurity ions are injected into the entire surface of the semiconductor substrate
11
using the gates
13
a
and
13
b
as masks, so that a Lightly Doped Drain (LDD) region is formed in the semiconductor substrate
11
corresponding to an active region at both sides of the gates
13
a
and
13
b.
AS shown in
FIG. 1B
, a first High temperature Low Deposition (HLD) film
15
and a nitride film (not shown) are sequentially deposited on the surface of the semiconductor substrate
11
, and a first Boron Phosphorus Silicate Glass (BPSG) film
16
is formed on the nitride film at a predetermined thickness.
Herein, the first BPSG film
16
is deposited by the flowing process at high temperature between 800° C. and 840° C.
As shown in
FIG. 1C
, a first photoresist
17
is deposited on the semiconductor substrate
11
, and the first photoresist
17
is selectively patterned by exposure and developing processes to open the logic region and the DRAM peripheral region.
Subsequently, the first BPSG film
16
on the logic region and the DRAM peripheral region is removed by a wet-etching process using the patterned first photoresist
17
as a mask, and then the first photoresist
17
is removed. In this case, the DRAM cell region in a boundary portion between the DRAM cell region and the DRAM peripheral region is partially etched by the wet-etching process.
As shown in
FIG. 1D
, the first HLD film
15
and the nitride film are selectively removed by an etch-back process to remain at both sides of the logic gate
13
a
and the DRAM gate
13
b
of the DRAM peripheral region, so that insulating film sidewalls
15
a
are formed by the first HLD film
15
.
Heavily doped impurity ions are injected into the entire surface of the semiconductor substrate
11
. Then, source and drain regions
18
and
19
are formed in the semiconductor substrate
11
corresponding to the active region at both sides of the insulating film sidewalls
15
a.
A second HLD film is deposited on the surface of the semiconductor substrate
11
to protect a cell region and an input/output (I/O) (not shown). Then, the second HLD film is selectively removed by photolithography and etching processes to remain only on the cell region and the I/O region.
As shown in
FIG. 1E
, cobalt is deposited on the entire surface of the semiconductor substrate
11
and then annealed, so that a cobalt silicide film
20
is formed on the surfaces of the logic gate
13
a,
the source region
18
, and the drain region
19
.
Herein, the cobalt silicide film
20
is formed on the surfaces of the logic gate
13
a,
the source region
18
and the drain region
19
by reacting silicon with cobalt. However, the DRAM gate
13
b
of the DRAM peripheral region consists of oxide films on an upper surface, so that the cobalt silicide film is not formed.
The remaining cobalt, which is not reacted with silicon, is then removed.
As a third HLD film
21
is deposited on the surface of the semiconductor substrate
11
, and a second BPSG film
22
is deposited by a flowing process at a low temperature. Then, a rapid thermal annealing (RPA) process is performed.
As shown in
FIG. 1F
, the surface of the second BPSG film
22
is flattened by a chemical mechanical polishing (CMP) process.
Subsequently, a fourth HLD film
23
is deposited on the second BPSG film
22
. Then, the fourth HLD film
23
, the second BPSG film
22
, the third HLD film
21
, the first BPSG film
16
and the first HLD film
15
are sequentially removed by photolithography and etching process to expose the semiconductor substrate
11
of the DRAM cell region corresponding to the active region, so that a trench is formed.
A plug poly is deposited on the entire surface of the semiconductor substrate
11
including the trench, and then etched back, so that a plug
24
is formed within the trench.
A fifth HLD film
25
is finally deposited on the semiconductor substrate
11
. Thus, the related art semiconductor device is completed.
However, the related art method for fabricating a semiconductor device has several problems.
First, since the logic region and the DRAM peripheral region are opened by the wet-etching process, the boundary portion of the DRAM cell region is etched in accordance with characteristic of the wet-etching process. Therefore, a defect occurs in the semiconductor device.
Also, since no insulating film sidewalls are formed at both sides of the DRAM gates corresponding to the DRAM cell region, gap-fill characteristic is deteriorated. For this reason, a void occurs in the plug.
Furthermore, the etching defects according to a DRAM cell area occur during forming the insulating film sidewalls, so that uniformity decreases, thereby increasing defects of the semiconductor device.
Finally, the application of the process for forming a cell capacitor process identical with the existing DRAM is impossible in the present invention. For this reason, characteristics related to self align margin (SAC), leakage, and capacitor are varied. This results in that the cell characteristic is not reliable. Therefore, the production yield decreases.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a semiconductor device that improves reliability of the device and the production yield.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the in
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
Thomas Toniai M.
Zarabian Amir
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