Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-26
2003-05-13
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S306000, C438S918000
Reexamination Certificate
active
06562686
ABSTRACT:
BACKGROUND
1. Technical Field
A method for fabricating a semiconductor device is disclosed. In particular, an improved method for fabricating a high speed semiconductor device is disclosed where the device includes a salicide. In the disclosed method, a shallow and a deep source/drain region are formed simultaneously by forming an insulating film spacer on sidewalls of a gate electrode, forming SEG (selective epitaxial growth) layer in the LDD (lightly doped drain) region adjacent to the insulating film spacer, and then performing an ion implanting process.
2. Description of the Related Art
In general, the most important function of a transistor of a semiconductor circuit is a current driving function. A channel width of a metal-oxide-semiconductor field effect transistor (MOSFET) is adjusted in consideration of the current driving function. In the most widely-used MOSFET, an impurity-doped polysilicon layer is used as a gate electrode, and a diffusion region formed by doping an impurity on a semiconductor substrate is used as a source/drain region.
A buried channel is formed in a P-type-semiconductor field effect transistor (PMOSFET) which uses an N+ doped polysilicon gate electrode in a complementary metal-oxide-semiconductor field effect transistor (CMOSFET). Here, because a N-type-semiconductor field effect transistor (NMOSFET) having a channel on its surface and the PMOSFET have different threshold voltages, there are various restrictions in design and fabrication of the device.
That is, in the CMOSFET using a dual gate electrode, the dual gate electrodes are formed by ion-implanting N-type and P-type impurities twice. Therefore, a photolithography process should be performed twice, and this complicates the fabrication process. Accordingly, the device can be easily contaminated due to a wet process, and thus the process yield and reliability thereof are reduced.
In addition, as the sizes of semiconductor devices becomes smaller, the junction depth becomes shallower. However, in high speed devices, large leakage current occurs due to the salicide process in which silicide layers are formed on the source/drain region and the gate electrode.
FIGS. 1A through 1C
are cross-sectional diagrams illustrating sequential steps of a conventional method for fabricating a semiconductor device.
First, referring to
FIG. 1A
, a field oxide
11
defining an active region is formed on a semiconductor substrate
10
. A gate oxide
12
and a polysilicon layer (not shown) are formed on the semiconductor substrate
10
. Thereafter, the polysilicon layer is etched using a gate electrode mask as an etching mask, to form a gate electrode
13
. An LDD region
14
is formed by ion-implanting a low concentration impurity to the semiconductor substrate
10
at both sides of or around the gate electrode
13
. An insulating film spacer
15
is formed on side walls of the gate electrode
13
.
As shown in
FIG. 1B
, a first source/drain region
16
is formed by ion-implanting a high concentration impurity to the semiconductor substrate
10
at both sides of or around the insulating film spacer
15
. Here, As is ion-implanted for a NMOS, and B
11
for a PMOS.
Thereafter, still referring to
FIG. 1B
, a second source/drain region
17
is formed by implanting a dopant having a high diffusion ratio at a low dose. Here, Ph is ion-implanted instead of As for a NMOS, and B
11
instead of BF
2
for a PMOS.
As seen in
FIG. 1C
, a silicide layer
18
is formed on the surfaces of the gate electrode
13
, the first source/drain region
16
and the second source/drain region
17
.
However, the conventional method for fabricating the semiconductor device has a limit due to shallow junction region resulting from miniaturization of the device. Therefore, increase in the depth of the junction region due to the ion implant process for forming the silicide layer
18
influences the LDD region
14
. Especially, when the silicide layer
18
is formed deeply along the rim of the field oxide layer
11
, leakage current increases considerably in the junction region of the field oxide
11
and the height of the field oxide
11
is decreased during subsequent processes. In addition, in case of a borderless contact, since the contact is formed along the rim of the field oxide
11
, leakage current drastically increases in the junction region of peripheral circuit region.
SUMMARY OF THE DISCLOSURE
Accordingly, a method for fabricating a semiconductor device is disclosed which can prevent increase in a junction leakage current and improve a process yield and reliability, by forming a protection film along the rim of the field oxide, forming a SEG layer on the source/drain region, removing the protection film and ion-implanting to form a deep junction in the source/drain region. As a result, the region where the protection film has a deeper junction than the region where the SEG layer is so the ion-implant process has no negative effect on the channel region of CMOS device.
A disclosed method for fabricating a semiconductor device comprises: forming an field oxide defining a active region in a semiconductor substrate; forming a gate oxide and a gate electrode on the active region of the semiconductor substrate; forming an LDD region by ion-implanting low concentration impurities in the semiconductor substrate at both sides of or around the gate electrode; forming an insulating film spacer on each sidewall of the gate electrode; forming a protection film pattern exposing the gate electrode, the insulating film spacer and a portion of the active region of the semiconductor substrate adjacent to the insulating film spacer; forming a SEG layer on the exposed portion of the active region of the semiconductor substrate; removing the protection film pattern; forming a source/drain region comprising a shallow highly dopes source/drain region (“shallow SID region”) and a deep highly doped source/drain region (“deep SID region”) by ion-implanting high concentration impurities, wherein the shallow SID region is formed beneath the SEG layer and the deep SID region is formed at the exposed active region adjacent to the field oxide where the SEG layer is not formed; forming a silicide layer on the gate electrode, the SEG layer and the active region of the semiconductor substrate.
The protection film pattern may be formed of one or more films selected from a group of silicon oxide film, silicon nitride film, silicon oxynitride film and combinations thereof.
The protection film pattern leaves an exposed portion of the LDD region ranging from about 0.01 to about 1 &mgr;m away from the insulating film spacer.
The SEG layer may have a thickness ranging from about 0.01 to about 0.5 &mgr;m.
The SEG layer may be a single crystal layer, an amorphous silicon layer or a phosphorous silicon layer.
A novel semiconductor device made in accordance with the disclosed methods is also disclosed.
REFERENCES:
patent: 5841173 (1998-11-01), Yamashita
patent: 5985722 (1999-11-01), Kishi
patent: 6110787 (2000-08-01), Chan et al.
patent: 6162689 (2000-12-01), Kepler et al.
patent: 6194748 (2001-02-01), Yu
patent: 6238989 (2001-05-01), Wc Huang et al.
patent: 6489206 (2002-12-01), Chen et al.
United Kingdom Search Report dated Dec. 10, 2002 (2 pages).
Brophy Jamie L.
Zarabian Amir
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