Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-21
2002-11-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000
Reexamination Certificate
active
06479336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device having a tungsten gate capable of being applied to a self-aligned contact process.
2. Description of the Related Art
As is well-known, gates are mainly made of polysilicon. This is because the polysilicon sufficiently meets desired properties required for gates, for example, high melting point, easy formation of thin films, easy patterning of lines, stability in an oxidation atmosphere, and formation of planarized surfaces. Where such polysilicon gates are practically applied to MOSFET devices, they obtain a desired resistance value by containing a dopant such as phosphorous (P), arsenic (As), or boron (B).
Meanwhile, an increased degree of integration for semiconductor devices results in a reduction in the value of a parameter, such as the line width of gates, the thickness of gate insulating films, or the junction depth in those semiconductor devices. For this reason, where highly integrated semiconductor devices are fabricated using polysilicon, it is difficult to realize the low resistance required in association with a micro line width. Thus, it is required to develop gates made of a new material substituted for polysilicon.
At the early stage of this development, active research and development efforts have been made in association with polycide gates made of a transition metal-silicide material.
However, such polycide gates have a limitation in realizing a low resistance due to the fact that polysilicon still remains in those gates. To this end, active research and development have recently been made in association with metal gates. Where such a metal gate is made of a metal having a work function value corresponding to the mid band-gap of silicon, it can be fabricated into a single gate usable for both the NMOS type and the PMOS type. The metal having a work function value corresponding to the mid band-gap of silicon may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (MO), tantalum (Ta), and tantalum nitride (TaN).
Where such a metal gate is practically applied to MOSFET devices, however, it has problems involved in the progression of processes, such as difficulty in etching a metal gate, damage applied to an associated silicon substrate during the etching process and thermal damage resulting from [a] thermal process conducted following the process.
For this reason, it is difficult to form such a metal gate using conventional gate formation processes. To this end, a method has been proposed in which metal gates are formed using a damascene process mainly used in the formation of metal lines.
Since this metal gate formation method using a damascene process does not involve an etching process, there is no damage generated in a silicon substrate, and a conventional MOSFET process can be used.
Now, a conventional method for fabricating MOSFET device having a tungsten gate using a damascene process will be described in conjunction with
FIGS. 1A
to
1
E.
Referring to
FIG. 1A
, a silicon substrate
1
provided with field oxide films
2
defining an active region is first prepared. A first thermal oxide film
3
is formed on the silicon substrate
1
to cover the active region and then a polysilicon film
4
and a hard mask film
5
are sequentially deposited over the field oxide film
2
and the first thermal oxide film
3
.
Referring to
FIG. 1B
, a hard mask pattern
5
a
defining a gate formation region is formed by patterning the hard mask film
5
in accordance with a well-known photolithography process. A polysilicon film
4
and a first thermal oxide film
3
are etched using the hard mask pattern
5
a
as an etch mask, as a result, a sacrificial gate
4
a
is formed. The resultant structure is subjected to a gate re-oxidation process, thereby forming a second thermal oxide film
6
on side walls of the sacrificial gate
4
a
and the exposed surface of the silicon substrate
1
. Subsequently, impurity ions having a desired conductivity are implanted at a low concentration into portions of the silicon substrate
1
, respectively arranged at opposite sides of the sacrificial gate
4
a
via the second thermal oxide film
6
. As a result, lightly doped drain LDD regions
7
are formed.
Referring to
FIG. 1C
, the second thermal oxide film is removed. A spacer
8
is formed on side walls of the sacrificial gate
4
a
and the hard mask pattern
5
a.
Impurity ions having a desired conductivity are implanted, at a high concentration into the silicon substrate
1
, thereby forming source/drain regions
9
on portions of the silicon substrate, respectively arranged at opposite sides of the sacrificial gate
4
a,
including the spacer
8
.
Referring to
FIG. 1D
, a interlayer insulating film
10
is deposited over the resultant substrate and thereafter, the interlayer insulating film
10
and the hard mask pattern
5
a
are polished in accordance with a CMP process using the sacrificial gate
4
a
as a polishing stop layer. The exposed sacrificial gate and the first thermal oxide film are removed to form a groove defining a region where a metal gate is to be formed. A gate insulating film
11
is formed to have a uniform thickness. Subsequently a metal film, for example a tungsten film
12
is deposited to completely film the groove.
Referring to
FIG. 1E
, a tungsten gate
12
a
is formed by polishing the tungsten film
12
and the gate insulating film
11
in accordance with a CMP process using the interlayer insulating film
10
as a polishing stop layer. Thus a MOSFET device having the tungsten gate
12
a
is obtained.
The tungsten gate
12
a
is capable of realizing a low resistance in association with a macro line width, and therefore it can be advantageously applied to fabricating highly-integrated devices.
However, it is difficult to apply the self aligned contact (SAC) process in a MOSFET device having the tungsten gate
12
a
due to the fact that there is no barrier film for the SAC process. For example, where there is a misalignment of a light exposure mask used, as shown in
FIG. 2
, an electric short circuit may occur between the tungsten gate
12
a
and the contact plug
15
. As a result, the MOSFET device has degraded reliability and degraded characteristics. Accordingly, it is difficult for the MOSFET device having the tungsten gate to be subjected to a SAC process. In
FIG. 2
, the reference numeral
14
denotes an insulating film.
As shown in
FIG. 3
, the electrical short circuit between the tungsten gate
12
a
and the contact plug
15
, is conventionally prevented by forming an SAC barrier film
13
made of a nitride film or a tungsten oxide film on the tungsten gate
12
a.
Here, The SAC barrier film
13
is obtained by sequentially following the steps of etching the tungsten gate, depositing a nitride film, and polishing the nitride film. The SAC barrier film made of the tungsten oxide film is formed by oxidizing the surface of the tungsten gate to a desired thickness.
However, the formation of the SAC barrier film made of nitride film results in an increase in the manufacturing time and cost of the MOSFET device because it necessarily involves additional processes. Consequently, there is a degradation in productivity, and as a result, it is difficult to practically apply this technique.
The formation of SAC barrier film made of the tungsten oxide film is comparatively simple. However, research efforts for reaction mechanisms and electrical characteristics are only at an early stage, so it is not preferable to use this film at the present time. Moreover, where the oxidation process of tungsten is carried out by furnace annealing, rapid thermal oxidation, N
2
O process or O
2
plasma process, even the effects on the formation of the tungsten oxide film and its resulting properties are not entirely understood.
As a result, unless that a new method for formatting a SAC barrier film on the tung
Dang Phuc T.
Hynix / Semiconductor Inc.
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