Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-05-27
2008-05-27
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S266000, C438S267000, C257SE21691
Reexamination Certificate
active
07378315
ABSTRACT:
A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.
REFERENCES:
patent: 6018178 (2000-01-01), Sung
patent: 6417086 (2002-07-01), Osari
patent: 6579762 (2003-06-01), Io
patent: 6677203 (2004-01-01), Kusumi et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Magnachip Semiconductor Ltd.
Trinh Michael
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