Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-23
2001-11-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06316322
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of forming source/drain regions in a semiconductor substrate, whereby a desired relationship between the impurity concentration peak and a lightly doped source/drain region is obtained. The present invention has particular utility in the manufacture of MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor devices require design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so called “short-channel” effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the, gate can cause gate oxide charging and threshold voltage and thus reduce instabilities. Shallow junction, lightly- or moderately-doped source drain extension-type transistor structures have been developed.
For p-channel MOS transistors, the major “short-channel” effects which limits performance arise from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS-type transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS- and CMOS-type devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by use of a pair of spacers on opposite sidewalls of the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
However, in the case of MOS and CMOS devices, formation of junctions having desired characteristics (e.g., the spatial relationship between the impurity concentration peak and the lightly- or moderately-doped source/drain region) is problematic.
Thus a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors which does not suffer from the above-described drawback associated with achieving a desired spatial relationship between the impurity concentration peak and the lightly- or moderately-doped source/drain region. Moreover, there exists a need for an improved process for fabricating transistor-based devices which permits capacitance between the lightly- or moderately-doped source/drain region and the semiconductor substrate to be modulated, which process is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-described drawback attendant upon conventional processing for forming submicron-dimensioned transistors for use in high-density integrated semiconductor devices, particularly in providing a process for forming a semiconductor device comprising a retrograde impurity profile having an impurity concentration peak wherein the distance between the depth of the peak and the lightly- or moderately-doped source/drain region can be precisely determined, thereby permitting modulation of the capacitance between the lightly- or moderately-doped source/drain region and the semiconductor substrate.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for forming a semiconductor device comprising a retrograde impurity profile having an impurity concentration peak wherein the distance between the depth of the peak and the lightly- or moderately-doped source/drain region can be precisely determined.
Another advantage of the present invention is a method of manufacturing a semiconductor device wherein capacitance between the lightly- or moderately-doped source/drain region and the semiconductor substrate can be modulated.
Additional advantages of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device on a wafer, which method comprises:
ion implanting an impurity of a first conductive type into a main surface of a semiconductor substrate to form a retrograde impurity profile having an impurity concentration peak at a first depth below the main surface;
forming a gate stack comprising a gate oxide formed on the main surface, a gate electrode formed on the gate oxide, and side wall spacers formed on side surfaces of said gate oxide and gate electrode;
selectively etching to remove the sidewall spacers and a preselected depth of a surface portion of said substrate; and,
ion implanting an impurity of a second conductive type into the etched surface of the substrate to form a lightly- or moderately-doped source/drain region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustrating of the best mode contemplated in carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
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Wolf, “Silicon Processing for the VLSI Era vol. 2: Process Integration”, pp. 389-391, Lattice Press, 1990.
Advanced Micro Devices , Inc.
Booth Richard
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