Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-04-28
2001-12-18
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S317000
Reexamination Certificate
active
06331377
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabricating method which can minimize a contact defect due to a global step difference on a wafer and secure a process margin of photolithography for forming a contact.
BACKGROUND OF THE INVENTION
With the higher integration of dynamic random access memory (DRAM) devices, it has been demanded to reduce a unit cell size. The most significant problem raised by the reduction in the cell size is to secure the capacitance of a capacitor. To secure the capacitance of the capacitor, various methods have been proposed, such as a method of reducing the thickness of a dielectric layer, a method of using a dielectric layer made of materials with high dielectric constant or a method of increasing the size of a storage electrode. Particularly, for an increase in the capacitance of the capacitor, the structure of the capacitor has been changed from an early plane structure to a stack- or trench-type structure. Further, in the stacked type capacitor structure, a technique has been changed to a cylinder-type capacitor structure or a fin-type capacitor structure to increase the valid area of the storage electrode.
Considering these technical changes in the light of a processing sequence, change has been made from a capacitor-under-bit line (hereinbelow referred to as a “CUB”) structure in which a capacitor is formed prior to the formation of the bit line, to a capacitor-over-bit line (hereinbelow referred to as a “COB”) structure in which a capacitor is formed after the formation of the bit line. The COB structure has an advantage over the CUB structure in that the capacitor can be formed regardless of the margin for a bit line forming process, thus increasing the capacitance of the capacitor in a limited area. That is, since the capacitor is formed over the bit line in the COB structure, the size of the storage electrode can be maximized to the limit of photolithography, enabling the formation of a capacitor with greater capacitance. However, in such a COB structure, the storage electrode of the capacitor is formed only at a memory cell region, thus increasing a global step difference on a wafer. That is, the absolute heights of a memory cell region where the capacitor is to be formed, a core region consisting of circuits for driving cells and a peripheral circuit region are different to one another, and this causes the reduction in a process margin of the photolithography for forming a metal contact.
FIGS. 1
to
3
are cross-sectional views for explaining a metal contact forming method of a DRAM device according to the prior art.
Referring now to
FIG. 1
, a field oxide film
12
is formed on a semiconductor substrate
10
, dividing the substrate
10
into an active region and a device isolation region. Subsequently, a first conductive layer
14
is deposited over the substrate
10
, patterned by photolithography, thus forming a gate electrode of a transistor acting as a word line. And then, source and drain regions (not shown) of the transistor are formed on the surface of the active regions at both sides of the gate electrode
14
.
After a first insulating layer
16
made of an insulating material like oxide is formed over the substrate
10
on which the transistor has been formed, the first insulating layer
16
is etched by photolithography, to form a bit line contact (not shown) to expose the drain region. Next, a second conductive layer
18
is deposited on the first insulating layer
16
containing the bit line contact and patterned by photolithography, thus forming a bit line which is connected to the drain region of the transistor via the bit line contact. A second insulating layer
20
made of an insulating material like BPSG (Boron-Phosphorus Silicate Glass) is formed on the second conductive layer
18
. The second insulating layer
20
serves to insulate the bit line from a storage electrode (not shown) of the transistor which is to be formed in a subsequent process, and for the planarization of the surface of the second insulating layer
20
, a flow process, an etch-back process or a chemical mechanical polishing (CMP) process is executed. Though not shown, the storage electrode of the transistor, a dielectric layer and a plate electrode are sequentially formed over the second insulating layer
20
. Next, to form a metal wiring of the active region (i.e., source/drain regions) and conductive layers, a photoresist
22
is formed over the whole surface of the resultant structure on which the capacitor has been formed. In a COB structured DRAM device, a vertical step difference among the memory cell region, a core region and a peripheral circuit region has already been formed due to the word line
14
and the bit line
18
before the capacitor is formed, so that even though the planarization is processed after the second insulating layer
20
is formed, it is impossible to remove the step difference of its lower structure. Hence, the thickness of the photoresist
22
varies by the area of the metal contact, as shown in FIG.
1
.
Referring to
FIG. 2
, the photoresist
22
is patterned by light-exposing and developing processes, thus forming a photoresist pattern
22
a
to open a metal contact region. Here, since the thickness of the photoresist
22
varies by the area of the metal contact as described above, in the case of placing a focus on the d, e and f-contact regions during the light-exposing process, the a and b-contact regions become out of focus and thus the critical dimensions (CD) of the a and b-metal contacts become reduced in the subsequent etching process.
Now, referring to
FIG. 3
, the second insulating layer
20
and the first insulating layer
16
are etched by using the photoresist patterns
22
a
as an etching mask, thus forming metal contact holes
24
. In this case, since the thickness of the photoresist
22
varies by the area of the metal contact, the critical dimension of the metal contact varies over 100 nm by the area of the metal contact due to the focus defect caused by the global step difference on the wafer during the etching process. That is, the critical dimension of the metal contact is gradually varied to the range of 100 to 200 nm or to be over 20% of a mean size of the contacts. Due to the variation of the critical dimension, there may occur a problem that the metal contact of small size is not opened, and in the case of increasing the size of all metal contacts to solve this problem, this generates another problem of causing a short between the word line
14
and the metal contact and reducing the overlap margin between the bit line
18
and the metal contact.
FIG. 4
is a graph showing the variation of the critical dimension (CD) of the metal contact according to the thickness (T
PR
) of the photoresist. From this graph, it is apparent that the critical dimension of the metal contact is reduced with the increase in the thickness (T
PR
) of the photoresist.
FIG. 5
is a graph showing the variation of the critical dimension of the metal contact according to the thickness of the photoresist which varies by the area of the metal contact. Here, a split wordline driver(SWD) region, a sense amplifier (S/A) region connected to each bit line, for amplifying a signal read from a cell, and a conjunction region for connecting blocks of the cell are the core region. And a row decoder (R/D) and a column decoder (C/D), each having a plurality of input terminals and a plurality of output terminals, are the peripheral circuit region. According to
FIG. 5
, S/A ACT(ACTIVE) refers to a sense amplifier active region; S/A B/P to a sense amplifier bitline poly region; S/A GP to a sense amplifier gate poly region; S/A EO to a sense amplifier equalizer region; SWD to a split wordline driver region; and CONJ to a conjunction structure.
Referring to
FIG. 5
, the critical dimension of the split wordline driver region where the distance between cells is the shortest is about 300 nm, that of the sense-amplifier region
Duda Kathleen
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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