Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-26
2001-03-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S272000, C438S289000, C438S389000
Reexamination Certificate
active
06204128
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device with an MOS structure.
In recent years, as the number of semiconductor devices integrated on a single chip has been tremendously increased, respective components of each semiconductor device have been drastically downsized. On the other hand, semiconductor devices are increasingly required to operate at an even higher speed and to demonstrate further improved reliability.
A semiconductor device with an MOS structure has heretofore been used for various type of electronic units and is also expected to find broader and broader applications from now on.
Hereinafter, a conventional method for fabricating a semiconductor device, more particularly a method for forming a gate electrode for an MOS transistor, will be described with reference to FIGS.
23
(
a
) and
23
(
b
).
First, as shown in FIG.
23
(
a
), a field oxide film
12
is formed by a LOCOS technique so as to surround a transistor-forming region
11
on a silicon substrate
10
. Thereafter, the surface of the silicon substrate
10
is thermally oxidized, thereby forming a silicon dioxide film
13
on the surface of the silicon substrate
10
. Next, a doped polysilicon film (not shown) is deposited by a CVD process over the entire surface of the silicon substrate
10
, and then a resist pattern (not shown, either) is defined on the polysilicon film. Subsequently, using the resist pattern as a mask, the polysilicon film is etched to form a gate electrode
14
. And source/drain regions
15
,
16
are formed.
Then, as shown in FIG.
23
(
b
), exposed portions of the silicon dioxide film
13
, which are located on right- and left-hand sides of the gate electrode
14
, are removed, thereby forming a gate insulating film
17
. Thereafter, an insulating film
18
is deposited over the entire surface of the silicon substrate
10
and planarized. Next, contact holes
19
,
20
and
21
are formed in the insulating film
18
to reach the gate electrode
14
, source region
15
and drain region
16
, respectively. Then, a conductive material is deposited to fill in these contact holes
19
,
20
and
21
and to slightly protrude upward therefrom. In this manner, electrode layers
22
,
23
and
24
are formed so as to be interconnected to the gate electrode
14
, source region
15
and drain region
16
, respectively.
As can be seen, according to the conventional method for fabricating a semiconductor device, when the gate electrode
14
is formed by etching a conductive film (i.e., the polysilicon film), the silicon dioxide film
13
is used as an etch stopper.
However, the larger the number of semiconductor devices integrated is, the thinner the gate insulating film of an MOS transistor tends to be. Thus, according to the conventional method, i.e., if a gate electrode is formed by patterning a conductive film using an insulating film to be a gate insulating film as an etch stopper, not only the conductive film to be etched away, but also the gate insulating film are removed unintentionally. As a result, the reliability of the gate insulating film deteriorates.
To make a semiconductor device with an MOS structure operate at a higher speed, the thickness of a gate electrode should be increased such that the gate electrode has its resistance reduced. However, if the thickness of the gate electrode is increased, i.e., if the aspect ratio of the gate electrode (which is a ratio of the thickness of the gate electrode to the width thereof) is increased, then the conductive film should be etched to a greater depth. Accordingly, it is more difficult to end the etching process exactly at the upper surface of the insulating film to be the gate insulating film. Stated otherwise, if the gate insulating film should be thin, then the aspect ratio of the gate electrode cannot be large and the resistance of the gate electrode cannot be sufficiently reduced. Nevertheless, when the aspect ratio of the gate electrode is set high, the aspect ratio of a contact hole, which is used to interconnect a doped layer formed within a semiconductor substrate, i.e., source/drain region, to an interconnection layer, should also be high. In such a situation, the process steps of forming the contact hole and filling in the contact hole with a conductive material cannot be performed just as originally designed, thus decreasing the reliability of the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is providing a method for fabricating a semiconductor device, by which the thickness of a gate insulating film can be reduced without sacrificing the reliability thereof and a gate electrode can be formed at a high aspect ratio.
To achieve this object, a method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a doped layer of a first conductivity type within a surface region of a semiconductor substrate; b) forming a recess by depositing an insulating film on the semiconductor substrate and then removing at least the insulating film in a region thereof where a gate electrode is to be formed; c) forming a gate insulating film on the surface of the semiconductor substrate, which is exposed inside the recess; and d) forming the gate electrode by filling in the recess with a conductive film.
According to the method of the present invention, after a gate insulating film has been formed on the surface of a semiconductor substrate, which is exposed inside a recess provided on the semiconductor substrate, a gate electrode is formed by filling in the recess with a conductive film. That is to say, since the gate electrode can be formed without using the gate insulating film as an etch stopper, it is possible to prevent the gate insulating film from being damaged during the formation of the gate electrode. Accordingly, the thickness of the gate insulating film can be reduced without sacrificing the reliability thereof, and the gate electrode can be formed at a high aspect ratio even when the thickness of the gate insulating film is reduced.
In one embodiment of the present invention, the method preferably further includes, between the steps b) and c), the step of e) forming a doped layer of a second conductivity type in a region under the bottom of the recess such that the doped layer of the first conductivity type is divided into two by the doped layer of the second conductivity type.
In such an embodiment, source/drain regions are formed out of the doped layer of the first conductivity type, which has been divided into two by the doped layer of the second conductivity type. Accordingly, the formation of a channel can be controlled by applying a voltage to the gate electrode to be formed over the doped layer of the second conductivity type, thus improving the reliability of the semiconductor device.
In another embodiment of the present invention, the step d) preferably includes the steps of: depositing the conductive film over the insulating film, as well as inside the recess; and removing portions of the conductive film that have been deposited on the insulating film, thereby forming the gate electrode such that the upper surfaces of the gate electrode and the insulating film are substantially flush with each other and planarized.
In such an embodiment, the upper surface of the insulating film, which will be an underlying layer in a subsequent process step, can be planarized when the gate electrode is formed. Accordingly, upper-level interconnects or devices can be formed on the insulating film, as well as on the gate electrode, without newly performing a planarization process step. Thus, a multilevel structure can be formed for the semiconductor device more easily.
In still another embodiment, the step b) preferably includes the step of forming the recess such that the bottom of the recess is located within the doped layer of the first conductivity type. The method preferably further includes, between the steps b) and c), the step of e) forming a doped layer of a second conductivity
Hayama Kazuo
Hibi Toshitaka
Malsawma Lex H.
Matsushita Electronics Corporation
Nixon & Peabody LLP
Robinson Eric J.
Smith Matthew
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