Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

1999-07-27

2001-01-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S304000

Reexamination Certificate

active

06180472

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device including self-aligned contacts.
In recent years, when contact members are formed to be interconnected to the source/drain regions of an MOS transistor, a self-aligned contact (SAC) structure is sometimes used to further increase the density of devices integrated on a chip. Specifically, in such a structure, a sidewall, which has been used for forming an LDD structure, is used again as an etch stopper for forming contacts in a self-aligned manner.
FIGS.
7
(
a
) through
7
(
d
) are cross-sectional views illustrating a conventional method for fabricating an MOS transistor with a known self-aligned contact structure. An LDD structure is often used recently for a transistor to meet the downsizing requirement. According to an ordinary method for fabricating such a transistor with an LDD structure, a sidewall is formed on a side of a gate electrode and heavily doped source/drain regions are formed by implanting ions into a substrate with that sidewall used as a mask.
First, in the process step shown in FIG.
7
(
a
), a gate oxide film
102
(e.g., a thermal oxide film), a polysilicon film
103
for forming a gate electrode and a silicon nitride film
104
are formed in this order on a semiconductor substrate
101
. And then a resist film
105
for patterning the gate is formed on the silicon nitride film
104
.
Next, in the process step shown in FIG.
7
(
b
), the silicon nitride film
104
and polysilicon film
103
are etched in this order using the resist film
105
as an etching mask, thereby forming an on-gate protective layer
104
a
and a gate electrode
103
a
. Thereafter, dopant ions are implanted into the semiconductor substrate
101
using the gate electrode
103
a
(and the on-gate protective layer
104
a
as a mask, thereby forming lightly-doped source/drain regions
106
. In this process step, phosphorus or arsenic ions are implanted to form an n-channel MOS transistor, or boron ions are implanted to form a p-channel MOS transistor. Then, a CVD oxide film
107
and a CVD nitride film
108
are deposited in this order over the substrate.
Subsequently, in the process step shown in FIG.
7
(
c
), the CVD oxide film
107
and CVD nitride film
108
are dryetched anisotropically to form an oxide sidewall
107
a
and a nitride sidewall
108
a
on a side of the gate electrode
103
a.
Thereafter, in the process step shown in FIG.
7
(
d
), dopant ions are implanted into the semiconductor substrate
101
using the gate electrode
103
a
and the oxide and nitride sidewalls
107
a
and
108
a
as a mask, thereby forming heavily-doped source/drain regions
109
. In this process step, phosphorus or arsenic ions are implanted to form an n-channel MOS transistor, or boron ions are implanted to form a p-channel MOS transistor. In this manner, an MOS transistor with an LDD structure is completed.
In a self-aligned contact structure, the nitride sidewall
108
a
formed in the above-described manner is used as an etch stopper in the process step of forming contact holes, thereby preventing the gate electrode from coming into electrical contact with the contact members.
FIG. 8
illustrates an exemplary cross section of an MOS transistor in which contact members have been formed. As shown in
FIG. 8
, an interlevel dielectric film
110
of silicon dioxide is deposited over the MOS transistor with the LDD structure shown in FIG.
7
(
d
), and then planarized. There
15
after, contact holes are formed in the interlevel dielectric film
110
by photolithography and etching techniques so as to reach the heavily-doped source/drain regions
109
. In this process step, even if part of a contact hole interferes with the on-gate protective layer
104
a
or the nitride sidewall
108
a
, the on-gate protective layer
104
a
or the nitride sidewall
108
a
is hardly etched. This is because the etch selectivity of the SiO
2
interlevel dielectric film
110
to the SiN on-gate protective layer
104
a
or the nitride sidewall
108
a
is high. In other words, since the on-gate protective layer
104
a
and the nitride sidewall
108
a
serve as an etch stopper in the process step of forming contact holes, the gate electrode
103
a
can be protected. Thereafter, the contact holes are filled in with plug electrodes
111
and an interconnection layer (not shown) is formed thereon.
The nitride sidewall
108
a
is used not only as an ion implant mask for forming the heavily doped source/drain regions
109
, but also as an etch stopper for protecting the gate electrode
103
a
in the process step of forming self-aligned contacts during the fabrication of an MOS transistor with SAC and LDD structures. However, it is already known that the direct contact of the nitride sidewall
108
a
with the side of the gate electrode
103
a
is likely to deteriorate the characteristics of the transistor. Thus, in the illustrated example, the thin oxide sidewall
107
a
is interposed between the gate electrode
103
a
and the nitride sidewall
108
a.
However, if a contact hole is formed to reach a region above the gate electrode
103
a
as shown in
FIG. 8
, then the upper edge of the oxide sidewall
107
a
is exposed inside the contact hole. And if that edge of the oxide sidewall
107
a
is etched away, then the resultant gap between the on-gate protective layer
104
a
and the nitride sidewall
108
a
is likely to be further removed. As a result, the contact hole might possibly reach the gate electrode
103
a
. That is to say, the plug electrode
111
as a contact member might be electrically shortcircuited with the gate electrode
103
a.
To solve such a problem, the process steps shown in FIGS.
9
(
a
) and
9
(
b
) are carried out after the MOS transistor has been formed by performing the process steps shown in FIGS.
7
(
a
) through
7
(
d
). Specifically, the MOS transistor is covered with a relatively thick CVD nitride film
112
, an interlevel dielectric film
110
is deposited over the entire surface of the substrate, and then contact holes are formed in the interlevel dielectric film
110
. In such a case, the progress of etching is blocked by the CVD nitride film
112
by the time the contact hole has gone through the interlevel dielectric film
110
as shown in FIG.
9
(
b
). Accordingly, it is possible to prevent the contact hole from reaching the gate electrode
103
a
with certainty.
The conventional process for fabricating a semiconductor device with an SAC structure, however, has the following drawbacks.
Specifically, if a relatively thick CVD nitride film
112
is deposited, then the gap between a pair of gate electrodes
103
a
for adjacent MOS transistors might be completely filled in with the CVD nitride film
112
as shown in FIG.
10
. In general, since the gate length and pitch have recently been reduced to about 0.15 &mgr;m and about 0.4 &mgr;m, respectively, the gap between the gates is as small as approximately 0.25 &mgr;m. In this particular LDD/SAC structure, the gap gets even smaller when taking the respective thicknesses of the oxide and nitride sidewalls into account. Accordingly, the gap is very likely to be totally filled in. In such a situation, it is virtually impossible to form such contact holes as reaching the source/drain regions
109
located under the gaps filled in with the CVD nitride film
112
as shown in FIG.
10
. This is because other members might be adversely affected if such contact holes are provided.
SUMMARY OF THE INVENTION
An object of the present invention is providing a method for fabricating a semiconductor device, which functions as an MIS transistor with an SAC structure and can contribute to device miniaturization, by forming self-aligned contacts while improving the reliability thereof.
A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a gate insulating film, a gate electrode and an on-gate protective layer in this order on a semiconductor substrate; b) implanting dopant ions into the se

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