Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-30
2004-08-31
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S310000, C438S311000, C438S422000, C257S295000, C257S296000
Reexamination Certificate
active
06784051
ABSTRACT:
FIELD OF THE INVENTION
This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2002-57755 filed in KOREA on Sep. 24, 2002, which is herein incorporated by reference.
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device capable of preventing a lifting of the pattern at an edge area of a wafer.
DESCRIPTION OF RELATED ARTS
As a degree of integration of a semiconductor device has been progressively advanced, there also present several accompanying problems. A bad pattern at an edge of a wafer is one example of the problems.
Hereinafter, a lifting of a wiring line occurring at wafer edges will be described by providing a preferred embodiment in connection with a process for forming a bit line pattern.
FIGS. 1A
to
1
D are cross-sectional views illustrating a process for forming a bit line in accordance with the prior art.
An inter-layer insulating layer
13
is deposited on a wafer
11
providing various elements for constituting a semiconductor device including a word line (not shown) and an impurity junction
12
. Herein, a word line insulating layer is another name for the inter-layer insulating layer
13
. The inter-layer insulating layer
13
is selectively etched to form a contact hole exposing the impurity junction
12
.
Continuously, a plug
14
for a bit line contact contacting to the impurity junction
12
exposed as burying the contact hole is formed. The plug
14
generally uses polysilicon. Currently, in addition to the polysilicon, a multi-stacked structure of tungsten and a barrier metal layer such as Ti/TiN is also increasingly used. In general, the Ti/TiN barrier metal layer is mainly used as a diffusion barrier layer.
The size of the contact hole becomes smaller close to the edge of the wafer
11
due to poor topology, and thus the width of the plug
14
also becomes thinner.
Next, a diffusion barrier layer
15
having a typical Ti/TiN structure for suppressing a reaction of a source gas with the plug
14
or the impurity junction
12
is formed on the plug
14
. The source gas is employed when depositing a metal layer for a bit line, e.g., tungsten. On top of the diffusion barrier layer
15
, a metal layer
16
for a bit line is formed by using a metal such as polysilicon and tungsten or a metal-alloy thin film such as tungsten nitride or tungsten silicide.
A buffer layer
17
is formed with the use of a an undoped silicate glass (USG) layer to reduce stress easily generated between the metal layer
16
and a subsequent nitride layer
18
used for a hard mask. Thereafter, the nitride layer
18
for a hard mask is deposited on the buffer layer
17
by applying a plasma enhanced chemical vapor deposition (PECVD) technique or a low pressure chemical vapor deposition (LPCVD) technique.
FIG. 1A
shows the state where the nitride layer
18
for a hard mask is deposited.
Referring to
FIG. 1B
, the nitride layer
18
, the buffer layer
17
, the metal layer
16
and the diffusion barrier layer
15
allocated at the edge area of the wafer are removed through the use of a wafer edge exposure (WEE) mask
19
in order to prevent a defect due to the metal layer
15
that can be remained at the edge area of the wafer in the course of a process for etching the nitride layer
18
, the buffer layer
17
, the metal layer
16
and the diffusion barrier layer
15
for forming a bit line. Herein, the above nitride layer
18
, the buffer layer
17
, the metal layer
16
and the diffusion barrier layer
15
are named bit line formation layers. At this time, the WEE mask
19
selectively opens a region, e.g., approximately 5 mm from the edge of the wafer for preparing an edge bead rinsing.
With reference to
FIG. 1C
, the bit line formation layers at the edge area of the wafer are removed, and then, the nitride layer
18
, the buffer layer
17
, the metal layer
16
and the diffusion barrier layer
15
are selectively etched by using a bit line etch mask so to form a bit line.
Referring to
FIG. 1D
, a nitride based material is deposited entirely on the above structure providing the bit line. An etch-back process is then performed to form a spacer
20
at lateral sides of the bit line.
An inter-layer insulating layer
21
is formed on the entire structure where the spacer is formed. Herein, a bit line insulating layer is another name for the inter-layer insulating layer
21
. In particular, the inter-layer insulating layer
21
typically uses a USG layer formed at a low temperature. The inter-layer insulating layer
21
is thinly deposited at an area
22
opened doubly in the WEE mask and the bit line mask processes. That is, in case that a high density plasma oxide (HDP) having a good gap fill property among the USG layers formed at a low temperature is deposited as the inter-layer insulating layer
21
, then, corners of the bit line close to the edge area of the wafer has a thinner deposition thickness based on deposition and etching mechanisms.
Subsequently, a chemical mechanical polishing (CMP) process for letting the inter-layer insulating layer
21
to be remained with a predetermined thickness on top of the nitride layer
18
is performed. At this time, a loss of a bit line pattern
23
near to the corners of the bit line is inevitable. Therefore, a lifting of the bit line pattern
23
occurs due to a thermal budget in a capacitor formation process carried out for fabricating a typical memory cell.
There have been many suggestions for improving the lifting of the bit line pattern. For instance, a bit line is formed at a point uniformly separated from the corners so as to be less affected by the loss of the inter-layer insulating layer
21
at the corners of the cell area when forming the bit line, or a material for the inter-layer insulating layer
21
is changed.
As shown in the lifting of the bit line pattern, a bad pattern at the edge of the wafer is caused by a global step difference due to a pattern density difference between a center and the edge of the wafer.
This global step difference becomes more severe because of a micronized pattern process. Thus, there have been researched on other approaches to cope with the global step difference.
The step difference between the center and the edge of the wafer becomes also severe due to the word line formation. As the pattern becomes micronized, topology at the edge of the wafer is degraded in more extents compared to the center of the wafer. Hence, a contact formation process for forming a bit line becomes more degraded at the edge of the wafer.
For instance, if a critical dimension (CD) of the contact hole in a 120 nm process is approximately 100 nm, the CD at the edge of the wafer is about 90 nm to 80 nm.
Since contacts at the center and the edge of the wafer have identical thickness but narrow width at the edge, an aspect ratio of the contact is inevitably larger at the edge of the wafer compared to the center of the wafer. Also, the lifting phenomenon at the edge of the wafer due to stress from a thermal budget and a material becomes even severe. Although the lifting phenomenon is not a major concern when the linewidth of the bit line is above about 100 nm, the lifting phenomenon becomes an issue in a process when the linewidth of the bit line is below about 100 nm.
In case that the pattern is collapsed or lifted at the edge area of the wafer, particles are generated. Accordingly, quality of a device is deteriorated and the particles penetrate into other normal wafer areas so as to induce a short circuit between electrodes.
The following will explain the lifting of the bit line at each area of the wafer.
In order to inspect the wafer, the wafer is classified with each die. It is observed that an area close to the center of the wafer and an area close to the edge of the wafer have different die shapes after completing an etching process for forming the bit line. Also, the contact hole size increases as being close to the center of the wafer. Thus, as close to the edge of the wafer
Hynix / Semiconductor Inc.
Wojciechowicz Edward
LandOfFree
Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3336174