Method for fabricating semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S301000, C438S308000, C438S770000

Reexamination Certificate

active

06835625

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims priority of Japanese Patent Application No. 2002-289938, filed on Oct. 2, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device having the step of activating a dopant by thermal processing.
The recent micronization of semiconductor devices makes it necessary that semiconductor device of MOS (Metal Oxide Semiconductor) transistors, etc. have shallow junctions. To this end, as a method of activation annealing following ion implantation of a dopant, RTA (Rapid Thermal Annealing) is used. RTA activates a dopant as much as possible by high-temperature heat processing in a short period of time while suppressing the diffusion of the dopant, whereby a lightly doped diffused layer is made thinner in a required concentration.
For example, in the MOS transistor fabricating process, a dopant is activated by RTA as the thermal processing in forming the lightly doped diffused layer of an LDD (Lightly Doped Drain) structure.
However, the micronization, etc. of semiconductor devices have thinned the gate insulation film in MOS transistor fabricating process. In order to suppress the generation of bird's beaks, the step of forming an oxide film for covering the surface of the substrate when ion implantation is performed tends to be omitted. Accordingly, in the thermal processing by RTA, out diffusion of an implanted dopant often takes place. The out diffusion of a dopant causes disadvantages of increase, deflection, etc. of the resistance of the shallow junction.
As a method for suppressing such out diffusion of a dopant, thermal processing is performed, e.g., by RTA in an oxygen added-atmosphere to thereby activate the dopant is proposed (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2000-114197). In this method, an oxide film is formed on a semiconductor substrate surface by rapid temperature increase in an oxygen added-atmosphere, whereby a dopant is activated while the out diffusion of the dopant can be suppressed.
Various methods for suppressing the out diffusion of a dopant by an oxide film formed by the thermal processing are proposed (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2000-277449 and Japanese Patent Application Unexamined Publication No. 2001-7220).
However, the above-described method, in which the temperature is rapidly increased in an oxygen added-atmosphere, can form an oxide film for suppressing the out diffusion but will often generate bird's beaks in gate electrodes. Influences produced by such birds' beaks will be unignorable as semiconductor devices are increasingly micronized. Even when the out diffusion of a dopant can be suppressed by an oxide film formed by thermal processing in an oxygen added-atmosphere, the bird's beaks generated in the gate electrodes simultaneously with the formation of the oxide film, which will resultantly cause deterioration of the transistor characteristics.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for fabricating a semiconductor device which, when a dopant is activated by thermal processing, can suppress the generation of bird's beaks while suppressing the out diffusion of the dopant.
According to one aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a gate electrode on a semiconductor substrate with a gate insulation film formed therebetween; implanting a dopant in the semiconductor substrate with the gate electrode as a mask to form a doped region in the semiconductor substrate; forming a chemical oxide film on the doped region, which prevents the dopant implanted in the doped region from diffusing outside the semiconductor substrate; and performing thermal processing for activating the dopant implanted in the doped region.
According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a gate electrode on a semiconductor substrate with a gate insulation film formed therebetween; implanting a dopant in the semiconductor substrate with the gate electrode as a mask to form a doped region in the semiconductor substrate; forming an oxide film by chemical vapor deposition at a film forming temperature of 250-500° C. on the doped region, which prevents the dopant implanted in the doped region from diffusing outside the semiconductor substrate; and performing thermal processing for activating the dopant implanted in the doped region.
As described above, according to the present invention, the gate electrode is formed on a semiconductor substrate with the gate insulation film formed therebetween, a dopant is implanted in the semiconductor substrate with the gate electrode as mask to form the doped region in the semiconductor substrate, the chemical oxide film which prevents the out diffusion of the dopant implanted in the doped region is formed on the doped region, and the thermal processing for activating the dopant implanted in the doped region is performed, whereby the out diffusion of the dopant implanted in the doped region can be suppressed. Thus, the doped diffused layer can have low resistance and the resistance value which is stable, whereby semiconductor devices of high reliability can be provided.
The thermal oxidation for activating the dopant implanted in the doped region is performed in an atmosphere containing no oxygen, whereby the generation of bird's beaks in the gate electrode area can be suppressed.


REFERENCES:
patent: 4434013 (1984-02-01), Bol
patent: 4621413 (1986-11-01), Lowe et al.
patent: 4727044 (1988-02-01), Yamazaki
patent: 5399506 (1995-03-01), Tsukamoto
patent: 6555439 (2003-04-01), Xiang et al.
patent: 6582998 (2003-06-01), Nitta
patent: 6583016 (2003-06-01), Wei et al.
patent: 2003/0003668 (2003-01-01), Oh
patent: 7-272990 (1995-10-01), None
patent: 2000-114197 (2000-04-01), None
patent: 2000-277449 (2000-10-01), None
patent: 2001-7220 (2001-01-01), None
patent: 2001-297996 (2001-10-01), None

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