Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-07
2004-06-22
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000
Reexamination Certificate
active
06753232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More specifically, it relates to an improved method for forming an ultra shallow junction in a PMOS device by positioning a screen oxide film to which an inert gas is ion-implanted between a gate electrode and a nitride film spacer.
2. Description of the Background Art
In current methods for making PMOS devices, nitride film spacers are used to obtain a channel length and protect an electrode. Stress differences between polysilicon and the nitride material cause problems, however. In order to solve this problem, an oxide film is formed between the nitride film spacer and the polysilicon. However, it is difficult to selectively deposit the oxide film on a predetermined portion.
The nitride film spacer is formed by depositing a nitride film on the oxide film, and performing a full etching process thereon. Thereafter, an impurity junction region is formed according to an ion implant process using the appropriate dopants. Here, defects of p-type dopants are generated due to low solubility in semiconductor substrates that are composed of silicon, and due to transient enhanced diffusion (TED) of the p-type dopants.
After the ion implant process for forming p+ source/drain regions, unwanted diffusion in the channel length direction and punch-through in the depth direction may occur. Diffusion by the p-type dopants reduces the effective channel length. Oxidative enhanced diffusion (OED) of the oxide film between the gate electrode and the nitride film spacer in the depth direction causes the punch-through.
Conventional PMOS devices employ a buried channel, which is a channel formed by a depletion mode in the channel region using n+ poly silicon layers. However, threshold voltage adjusting dopants and junction forming dopants can diffuse in the depth direction due to the TED phenomenon during a succeeding annealing process. This can also deterioratethe quality of the gate insulating film.
Alternatively, p+ source/drain regions in PMOS transistors have been formed using BF
2
ions. However, F
19
ions in BF
2
ions also reduce quality of the gate insulating film. Specifically, F
19
ions are impurities that can cause defects in the transistor. For instance, F
19
ions can form a thin film between the oxide films deposited between the gate electrode and the nitride film spacer. This can reduce a stress resulting from the gate insulating film and the nitride film spacer for protecting the gate electrode. In addition, such growth defects can generate leakage current during the succeeding annealing process. Because the ion implant process for forming the p+ source/drain regions using BF
2
exposes the transistor to F
19
impurities, such problems from F
19
impurities are unavoidable.
SUMMARY OF THE INVENTION
The present invention provides an improved method for fabricating a semiconductor device. The method comprises forming a stabilized junction by simultaneously adjusting diffusion in a channel direction and a depth direction by restricting transient enhanced diffusion and oxidation enhanced diffusion, and reducing a short channel effect and diffusion in the depth direction, by positioning a nitrified oxide film between a gate electrode and a nitride film spacer formed at side walls of the gate electrode. The process helps to remove defects generated due to stress differences between the gate electrode and the nitride film spacer in a formation process of a PMOS transistor. It is thus possible to form a device having an ultra shallow junction which is not influenced by miniaturization.
The improved method comprises:
forming a gate insulating film on a semiconductor substrate;
forming a gate electrode on the gate insulating film;
forming a screen oxide film over the resulting structure;
implanting nitrogen ions to the screen oxide film;
depositing a nitride film for a spacer on the screen oxide film, and simultaneously performing an annealing process to nitrify the screen oxide film in which the nitrogen ions are implanted;
forming a spacer comprising the nitrified screen oxide film and the nitride film at side walls of the gate electrode, by removing the nitride film for the spacer and the nitrified screen oxide film; and
forming p+ source/drain regions on the semiconductor substrate at both sides of the spacer.
In an embodiment of the present invention, the gate insulating film is formed at a thickness of 40 to 100 Å according to a wet oxidation process using hydrogen and oxygen at a temperature of 750 to 800° C., and to an annealing process in a nitrogen atmosphere of 800 to 950° C. for 20 to 30 minutes.
The gate electrode has a stacked structure of a p-type polysilicon layer, WNx layer and W layer.
The p-type polysilicon layer may be formed at a thickness of 700 to 1000 Å according to a low pressure chemical vapor deposition (LPCVD) process using a silicon source gas such as SiH
4
or Si
2
H
6
and POCl
3
or PH
3
gas at a temperature of 510 to 550° C. under a pressure of 0.1 to 3.0 Torr.
The screen oxide film may be formed at a thickness of 100 to 150 Å according to the LPCVD process using a mixed gas of nitrogen, oxygen and hydrogen gases at a temperature of 600 to 750° C.
The ion implant process may be performed using dopant of 1×10
14
to 3×10
15
ions/cm
2
at a tilt of 30 to 60° C. with an ion implant energy of 0.5 to 5 keV.
The nitride film for the spacer may be deposited according to a chemical vapor deposition (CVD) process using NH
3
and DCS.
The p+ source/drain regions may be formed according to an ion implant process using BF
2
of 1×10
14
to 3×10
15
ions/cm
2
with an ion implant energy of 5 to 25 keV.
A rapid thermal process may be performed on the p+ source/drain regions in a nitrogen atmosphere of 800 to 950° C. increased at a speed of 50 to 150° C. after the ion implant process.
The principle of the present invention is to form the PMOS having a ultra shallow junction region by removing defects due to F
19
included in the screen oxide film formed between the gate electrode and the nitride film spacer by nitrifying the screen oxide film.
REFERENCES:
patent: 5237188 (1993-08-01), Iwai et al.
patent: 5648287 (1997-07-01), Tsai et al.
patent: 6171889 (2001-01-01), Iwamatsu et al.
patent: 6555438 (2003-04-01), Wu
Kwak Noh-yeal
Park Sang Wook
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hynix / Semiconductor Inc.
Pham Long
Trinh (Vikki) Hoa B.
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