Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-11-01
2004-12-14
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S761000, C438S762000, C438S279000
Reexamination Certificate
active
06831020
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a MOS semiconductor device having three types of gate insulating films of different thicknesses.
Conventionally, a process in which two types of gate insulating films having different thicknesses are formed selectively on one chip has been used commonly for a MOS semiconductor device. In the generation of 0.18-&mgr;m design rules, e.g., a MOSFET having a thin-film gate insulating film with a thickness of about 3.5 nm has been provided for an internal circuit operating at 1.8 V, while a MOSFET having a thick-film gate insulating film with a thickness of about 8 nm has been provided for an input/output circuit operating at 3.3 V (see pp.2-3 and
FIGS. 1A
to
1
H of Japanese Laid-Open Patent Publication No. HEI 1-168054).
FIGS. 13A
to
13
C are cross-sectional views illustrating the individual process steps of a method for fabricating a semiconductor device according to a first conventional embodiment, specifically a method for fabricating a MOS semiconductor device having two types of gate insulating film having different thicknesses.
First, as shown in
FIG. 13A
, a heat treatment is performed in an oxidizing atmosphere with respect to a silicon substrate
10
having the active region of the MOSFET for the internal circuit (hereinafter referred to as the internal MOSFET active region) and the active region of the MOSFET for the input/output circuit (hereinafter referred to as the input/output MOSFET active region). As a result, a surface of the silicon substrate
10
is thermally oxidized so that a first gate insulating film
11
having a thickness of about 6 nm is formed on each of the internal MOSFET active region and the input/output MOSFET active region.
Next, as shown in
FIG. 13B
, wet etching using a solution containing a hydrofluoric acid is performed with respect to the first gate oxide film
11
by using a resist pattern
12
covering the input/output MOSFET active region as a mask, thereby removing the first gate oxide film
11
on the internal MOSFET active region therefrom. This exposes the substrate surface in the internal MOSFET active region.
After the resist pattern
12
is then removed, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate
10
, as shown in FIG.
13
C. Since the first gate oxide film
11
has been formed on the input/output MOSFET active region, the substrate surface in the internal MOSFET active region is thermally oxidized. This allows a second gate oxide film
13
having a thickness of about 3.5 nm to be formed on the internal MOSFET active region. On the other hand, the first gate oxide film
11
is increased in thickness to about 8 nm. Accordingly, the second gate oxide film
13
is thinner than the first gate oxide film
11
that has been increased in thickness.
Thereafter, a gate electrode, source/drain electrodes, an interlayer insulating film, metal wiring, and the like are formed by using well-known techniques, though they are not depicted, whereby the fabrication of the semiconductor device comprising the input/output MOSFET having the relatively thick first gate oxide film
11
and the internal MOSFET having the relatively thin second gate oxide film
13
is completed.
As the gate insulating film of the internal circuit is reduced in thickness with the miniaturization of the MOSFET, however, the power consumption of the internal circuit of the first conventional embodiment tends to increase due to an increased gate leakage current. Consequently, it has become difficult to enhance the performance of a MOS semiconductor device represented by a system LSI, while reducing both of the size (increasing the degree of integration) and power consumption thereof.
To reduce both of the size and power consumption of the internal circuit, there has been examined a method of constituting the internal circuit by two MOSFETs, one of which is a MOSFET wherein an enhanced driving ability achieved by a reduction in the thickness of the gate insulating film is a higher priority and the other of which is a MOSFET wherein reduced power consumption is a higher priority, and selectively using the two MOSFETs depending on an object or a use. In suppressing an increase in power consumption resulting from a gate leakage current, it is most effective to increase the thickness of the gate insulating film. It becomes therefore necessary to individually form two types of gate insulating films having different thicknesses. In the generation of 0.10-&mgr;m design rules, e.g., size reduction and lower power consumption can be achieved by using a thin-film gate insulating film with a thickness of 1.6 nm and a thick-film gate insulating film with a thickness of 2.4 nm as the gate insulating films of a MOSFET composing an internal circuit operating at 1.0 to 1.2 V. On the other hand, an input/output circuit required to operate at a high voltage of 3.3 V, 2.5 V, or the like needs a MOSFET having a gate insulating film with a thickness of about 8 nm. Thus, it has become necessary to individually form the total of three gate insulating films having different thicknesses for the internal circuit and the input/output circuit in one chip.
To implement the three types of gate insulating films formed individually, there has been proposed a method for fabricating a semiconductor device using three thermal oxidation steps (see pp. 79-80 (especially
FIG. 2
) of A. Ono et al., A Multi-gate Dielectric Technology Using Hydrogen Pre-treatment for 100 nm generation System-on-a-Chip, 2001 Symposium on VLSI Technology Digest of Technical Papers).
FIGS. 14A
to
14
C and
FIGS. 15A
to
15
C are cross-sectional views illustrating the individual process steps of a method for fabricating a semiconductor device according to a second conventional embodiment, specifically a method for fabricating a MOS semiconductor device having three types of gate insulating films of different thicknesses.
First, as shown in
FIG. 14A
, an isolating region (not shown) is formed in silicon substrate
20
by LOCOS or the like so as to partition the silicon substrate
20
into an input/output MOSFET active region, a first internal MOSFET active region, and a second internal MOSFET active region. Then a mask nitride film and a pad oxide film (each of which is not shown) used for the formation of the isolation region are removed by wet etching, whereby a substrate surface in each of the MOSFET active regions is exposed.
Next, as shown in
FIG. 14B
, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate
20
having the input/output MOSFET active region, the first internal MOSFET active region to be provided with a thick-film gate insulating film, and the second internal MOSFET active region to be provided with a thin-film gate insulating film. This thermally oxidizes a surface of the silicon substrate
20
and thereby allows a first gate oxide film
21
to be formed individually on each of the input/output MOSFET active region, the first internal MOSFET active region, and the second internal OSFET active region.
Next, as shown in
FIG. 14C
, wet etching using a solution containing a hydrofluoric acid is performed with respect to the first gate oxide film
21
by using, as a mask, a first resist pattern
22
covering the input/output MOSFET active region, thereby removing the first gate oxide film
21
on each of the first and second internal MOSFET active regions therefrom and exposing the substrate surface in each of the first and second internal MOSFET active regions.
After the first resist pattern
22
is then removed, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate
20
, as shown in FIG.
15
A. Since the first gate oxide film
21
has been formed on the input/output MOSFET active region, the substrate surface in each of the first and second internal MOSFET active regions is thermally oxidized. This allows a second gate oxide film
23
to be formed individually on each of the first and second i
Nakaoka Hiroaki
Yamada Takayuki
Everhart Caridad
McDermott Will & Emery LLP
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