Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-17
2002-11-05
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S594000
Reexamination Certificate
active
06475863
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flash memory technology, and more particularly, to a method for fabricating a self-aligned flash memory cell with dimensions that are beyond photolithography limitations and with minimized bit line to bit line leakage current and with maximized area of drain and source bit line silicides.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a flash memory cell
100
of a flash memory device includes a tunnel dielectric structure
102
typically comprised of silicon dioxide (SiO
2
) as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure
102
is disposed on a semiconductor substrate or a p-well
103
. In addition, a floating gate structure
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure
102
. A floating dielectric structure
106
, typically comprised of silicon dioxide (SiO
2
), is disposed over the floating gate structure
104
. A control gate structure
108
, comprised of a conductive material, is disposed over the floating dielectric structure
106
.
A drain bit line junction
110
that is doped with a bit line dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area
112
of the semiconductor substrate or p-well
103
toward a left sidewall of the tunnel dielectric structure
102
in
FIG. 1. A
source bit line junction
114
that is doped with the bit line dopant is formed within the active device area
112
of the semiconductor substrate or p-well
103
toward a right sidewall of the tunnel dielectric structure
102
of FIG.
1
.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or tunneled out of the floating gate structure
104
. Such variation of the amount of charge carriers within the floating gate structure
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell
100
for example, a voltage of +9 Volts is applied on the control gate structure
108
, a voltage of +5 Volts is applied on the drain bit line junction
110
, and a voltage of 0 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are injected into the floating gate structure
104
to increase the threshold voltage of the flash memory cell
100
during programming of the flash memory cell
100
.
Alternatively, during erasing of the flash memory cell
100
, a voltage of −9.5 Volts is applied on the control gate structure
108
, the drain bit line is floated at junction
110
, and a voltage of +4.5 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
for example. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate structure
104
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of −9.5 Volts is applied on the control gate structure
108
and a voltage of +9 Volts is applied on the semiconductor substrate or p-well
103
with the drain and source bit line junctions
110
and
114
floating. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate structure
104
to the substrate or p-well
103
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
.
The tunnel dielectric structure
102
, the floating gate structure
104
, the floating dielectric structure
106
, and the control gate structure
108
comprise the gate structure of the flash memory cell
100
. Such structures and operation of the flash memory cell
100
, are known to one of ordinary skill in the art of flash memory technology.
Referring to
FIG. 2
, in the prior art, for forming the gate structure of the flash memory cell
100
, a layer of tunnel dielectric material
122
, comprised of silicon dioxide (SiO
2
) for example, is deposited on the semiconductor substrate
103
. In addition, a layer of floating gate material
124
, comprised of polysilicon for example, is deposited on the layer of tunnel dielectric material
122
, and a layer of floating dielectric material
126
, comprised of silicon dioxide (SiO
2
) for example, is deposited on the layer of floating gate material
124
. Furthermore, a layer of control gate material
128
, comprised of polysilicon for example, is deposited on the layer of floating dielectric material
126
.
Referring to
FIGS. 2 and 3
, a photoresist structure
130
comprised of photoresist material is patterned on the layer of control gate material
128
. Referring to
FIG. 3
, any portions of the layer of control gate material
128
not under the photoresist structure
130
is etched away to form the control gate structure
108
comprised of the control gate material remaining under the photoresist structure
130
. Similarly, any portions of the layer of floating dielectric material
126
not under the photoresist structure
130
is etched away to form the floating dielectric structure
106
comprised of the floating dielectric material remaining under the photoresist structure
130
. In addition, any portions of the layer of floating gate material
124
not under the photoresist structure
130
is etched away to form the floating gate structure
104
comprised of the floating gate material remaining under the photoresist structure
130
. Furthermore, any portions of the layer of tunnel dielectric material
122
not under the photoresist structure
130
is etched away to form the tunnel dielectric structure
102
comprised of the tunnel dielectric material remaining under the photoresist structure
130
.
Processes for deposition and patterning of the layer of tunnel dielectric material
122
, the layer of floating gate material
124
, the layer of floating dielectric material
126
, and the layer of control gate material
128
, with the photoresist structure
130
to form the gate structure comprised of the tunnel dielectric structure
102
, the floating gate structure
104
, the floating dielectric structure
106
, and the control gate structure
108
, are known to one of ordinary skill in the art of flash memory technology.
Referring to
FIGS. 3 and 4
, after such patterning of the gate structure comprised of the tunnel dielectric structure
102
, the floating gate structure
104
, the floating dielectric structure
106
, and the control gate structure
108
, the photoresist structure
130
is etched away. In addition, a bit line dopant, such as phosphorous or arsenic for an N-type dopant, is implanted into exposed regions of the active device area of the semiconductor wafer
103
to form the drain bit line junction
110
and the source bit line junction
114
. Such an implantation process for formation of the drain and source bit line junctions
110
and
114
is known to one of ordinary skill in the art of flash memory technology.
Then, spacers
132
, comprised of a dielectric material such as silicon dioxide (SiO
2
) for example, are formed on the sidewalls of th
Advanced Micro Devices , Inc.
Chaudhari Chandra
Choi Monica H.
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