Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-05
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S586000, C438S589000
Reexamination Certificate
active
06303448
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of elevated source and drain structures.
2) Description of the Prior Art
Under current MOSFET technology, raised source/drain regions are used in order to provide a transister having ultra-shallow junctions. Short channel effects increase as the source/drain depth increases, with respect to the gate oxide/silicon substrate interface. In order to minimize the source/drain depth raised source/drain regions are formed, typically using an epitaxial silicon process. The epitaxial growth of raised source/drain regions in MOSFET fabrication gives rise to numerous problems. The epitaxial growth of source and drain regions leaves facets or voids at the interfaces with the spacers formed adjacent to the gate and the interfaces with the field oxide regions. During the salicide process, silicide spikes are formed into these facets causing junction leakage. Another problem with the epitaxial growth of raised source/drain regions is diffusion of junction or lightly doped drain region (LDD) impurities during epitaxial growth. Yet another problem with epitaxial growth of raised source/drain regions is poor robustness and process yield due to difficulty controlling the thickness of the epitaial layer. Finally, the epitaxial growth of raised source/drain regions is an expensive process.
An alternative approach is disclosed by U.S. Pat. Nos. 5,079,180 & 5,198,378 (Rodder), whereby a thin spacer is formed adacent to the gate to allow for ion implant (I/I) after epitaxial growth of raised source/drain regions, while still allowing for sufficient horizontal migration of impurity ions to underlap the gate oxide. These patents also discloses formation of additional spacers in the abovementioned facets. This process does not solve the robustness issue caused by poor control of the thickness of the epitaxial layer nor does it alleviate the expense of epitaxial growth of raised source/drain regions. Also, this process relies on a timed etch in forming the additional spacers, again introducing a robustness issue as this process is also difficult to control.
Another alternative approach is disclosed by U.S. Pat. No. 5,312,768 (Gonzolez), whereby a layer of titanium nitride is deposited over the source/drain regions which acts as a barrier to impurity (phospherous or boron) outdiffusion. However, this process requires additional photo masks and a sputtering process which are expensive and complicated and reduce yields.
Yet another alternative approach is disclosed by U.S. Pat. No. 5,672,530 (Hsu), whereby raised polycrystalline silicon regions are deposited on previously deposited insulating layers, however this process is complicated and expensive due to numerous photo masking and etching steps. Also, the multiple photo masking and etching steps cause control and yield problems.
Alternatively, U.S. Pat. No. 5,641,694 (Kenney) shows a SIO transistor formed in a trench with the source and drain regions on the sidewalls.
U.S. Pat. No. 5,049,515 (Tzeng) shows an EEPROM having a drain region formed in a trench.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the aforementioned US patents.
SUMMARY OF THE INVENTION
It is an object of the present invention to acheive the performance advantages of ultra-shallow juntions in MOSFET devices.
It is another object of the present invention to reduce or eliminate juntion leakage problems associated with the salicide process on devices having ultra-shallow junctions.
It is another object of the present invention to reduce or eliminate the impurity ion diffusion problem associated with an epitaxial process.
It is another object of the present invention to eliminate the need for pre-amorpization of the polysilicon in the source/drain regions.
It is another object of the present invention to provide an economical and robust process for manufacturing MOSFET devices.
It is yet another object of the present invention to reduce resistance by implanting deeper LDD region while maintaining the performance advantages of ultra-shallow junctions.
To accomplish the above objectives, the present invention provides a method for fabricating elevated and drain structures on a substrate. The process begins by forming a first insulating layer (
12
) over a silicon substrate (
10
). A first barrier layer (
14
) is formed over the first insulating layer (
12
). A photoresist mask (
16
) having a first opening (
20
) is formed over the first barrier layer (
14
). The first barrier layer (
14
), the first insulating layer (
12
) and the silicon substrate (
10
) are dry etched through the first opening (
20
) in the photoresist mask (
16
) to form a trench (
50
) having the silicon substrate (
10
) as its bottom surface. Ions are implanted into the substrate (
10
) in the trench (
50
). Optionally, a second sacrificial oxide layer (
60
) can be formed, then removed to round sharp corners in the substrate (
10
) in the trench (
50
). A gate oxide layer (
62
) is formed on the substrate (
10
) in the trench (
50
). A polysilicon layer (
64
) is formed over the gate oxide layer (
62
) and the barrier layer (
14
). The polysilicon layer (
64
) is planarized using a chemical mechanical polishing process (CMP) to form a novel recessed gate (
64
A). The barrier layer can act as a CMP stop. The barrier layer (
14
) is removed by a selective etching process. The first insulating layer (
12
) is removed by a selective etching process. Lightly doped source/drain regions (LDD) (
66
) are formed adjacent to the recessed gate (
64
A). Spacers (
68
) are formed on the sidewalls of the recessed gate (
64
A). Source and drain regions (
70
) are formed adjacent to the spacers (
68
). Salicide layers (
72
,
74
) are formed on the source and drain regions (
70
) and on the top of the recessed gate (
64
A).
BENEFITS
The junction leak problem typical of salicided ultra-shallow juctions can be reduced because there are no voids in which salicide spikes can form into the substrate. In the prior art, epitaxial groxth of raised source/drain regions results in facets. In the present invention the source/drain are formed in the substrate, which is raised with respect to the gate because of the novel recessed gate.
By raising the source/drain regions with respect to the novel recessed gate, additional disadvantages of the epitaxial process are avoided. The impurity ion diffusion problem associated with an epitaxial process is reduced. The need for pre-amorpization of the polysilicon in the source/drain regions is eliminated. Additional, expensive, photo-masking steps and timed etching steps are avoided.
The novel recessed gate allows the present invention to reduce resistance by implanting thicker LDD regions while maintaining the performance advantages of ultra-shallow junctions. These thicker LDD regions allow a thicker silicide to be formed while still maintaining a sufficient distance between the silicide and the channel.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4839306 (1989-06-01), Wakamatsu
patent: 5049515 (1991-09-01), Tzeng
patent: 5079180 (1992-01-01), Rodden et al.
Chang Shou-Zen
Tsai Chao-Chieh
Ackerman Stephen B.
Gurley Lynne A.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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